CS61535A-IL1 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS61535A-IL1

T1/E1 Line Interface

Cirrus Logic 

CS61535A

locked VT operation, Table A1 shows potential

sub-multiple data rates, and the impact on those

rates on the maximum gap in the output clock of

the FIFO, and depth of FIFO required. FIFO

depth will have to be increased for floating VT

operation, with 8 bits of FIFO depth being added

for each pointer alignment change that can occur.

The objective that should be met in picking a

FIFO depth and clock divider is keep the maxi-

mum gap on the output of the FIFO at 12 bits or

less. Twelve bits is the maximum jitter which can

be input to the CS61535A’s jitter attenuator with-

out causing the overflow/undeflow protection

circuit to operate. The CS61535A then removes

the remaining jitter from the signal.

The receive path also requires a bit mapping

(from 193 or 256 bits to 6480 bits). This mapping

requires an input buffer with the same depth as

use on the transmit path. This buffer also absorbs

the output jitter generated by the CS61535A’s

digital clock recovery.

Target Rate

(MHz)

1.544

1.544

2.048

Clock

Divider

32

33

25

Resultant

Rate (MHz)

1.620

1.571

2.074

Transformers

Recommended transmitter and receiver trans-

former specifications for the CS61535A are

shown in Table A2. The transformers in Table A3

have been tested and recommended for use with

the CS61535A. Refer to the "Telecom Trans-

former Selection Guide" for detailed schematics

which show how to connect the line interface IC

with a particular transformer.

In applications with the CS61535A where it is ad-

vantageous to use a single transmitter transformer

for both 75Ω and 120Ω E1 applications, a 1:1.26

transforer may be used. Although transmitter re-

turn loss will be reduced for 75Ω applications, the

pulse amplitude will be correct across a 75 Ω

load.

Maximum Gap

(µs)

bits

6.2

10

3.9

6

3.4

7

FIFO Depth

Required

21

26

34

Table A1. Locked VT FIFO Analysis

Parameter

Turns Ratio

Primary Inductance

Primary Leakage Inductance

Secondary Leakage Inductance

Interwinding Capacitance

ET-constant

CS61535A Receiver

1:2 CT ± 5%

600 µH min. @ 772 kHz

1.3 µH max. @ 772 kHz

0.4 µH max. @ 772 kHz

23 pF max.

16 V-µs min. for T1

12 V-µs min. for E1

CS61535A Transmitter

1:1 ± 1.5 % for 75 Ω E1

1:1.15 ± 5 % for 100 Ω T1

1:1.26 ± 1.5 % for 120 Ω E1

1.5 mH min. @ 772 kHz

0.3 µH max. @ 772 kHz

0.4 µH max. @ 772 kHz

18 pF max.

16 V-µs min. for T1

12 V-µs min. for E1

Table A2. Transformer Specifications

DS40F2

33

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