LH28F160S5HB-L70 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F160S5HB-L70

16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)

Sharp Electronics 

LH28F160S5-L/S5H-L

Table 3 Command Definitions (NOTE 10)

COMMAND

BUS CYCLES

FIRST BUS CYCLE

SECOND BUS CYCLE

REQ’D. NOTE Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)

Read Array/Reset

Read Identifier Codes

Query

Read Status Register

1

Write

X

FFH

≥2

4

Write

X

90H

Read

IA

ID

≥2

Write

X

98H

Read

QA

QD

2

Write

X

70H

Read

X

SRD

Clear Status Register

1

Write

X

50H

Block Erase Setup/Confirm

2

5

Write

BA

20H

Write

BA

D0H

Full Chip Erase Setup/Confirm

2

Word/Byte Write Setup/Write

2

Write

X

30H

Write

X

D0H

5, 6 Write

WA

40H

Write

WA

WD

Alternate Word/Byte Write

Setup/Write

2

5, 6 Write

WA

10H

Write

WA

WD

Multi Word/Byte Write

Setup/Confirm

Block Erase and (Multi)

Word/Byte Write Suspend

≥4

9

Write

WA

E8H

Write

WA

N–1

1

5

Write

X

B0H

Confirm and Block Erase and

1

(Multi) Word/Byte Write Resume

5

Write

X

D0H

Block Lock-Bit Set

Setup/Confirm

2

7

Write

BA

60H

Write

BA

01H

Block Lock-Bit Reset

Setup/Confirm

2

8

Write

X

60H

Write

X

D0H

STS Configuration

Level-Mode for Erase

2

and Write (RY/BY# Mode)

Write

X

B8H

Write

X

00H

STS Configuration

2

Pulse-Mode for Erase

Write

X

B8H

Write

X

01H

STS Configuration

2

Pulse-Mode for Write

STS Configuration Pulse-Mode

2

for Erase and Write

Write

X

B8H

Write

X

02H

Write

X

B8H

Write

X

03H

NOTES :

1. Bus operations are defined in Table 2.1 and Table 2.2.

5. If the block is locked, WP# must be at VIH to enable

2. X = Any valid address within the device.

block erase or (multi) word/byte write operations.

IA = Identifier code address : see Fig. 2.

Attempts to issue a block erase or (multi) word/byte write

QA = Query offset address.

to a locked block while RP# is VIH.

BA = Address within the block being erased or locked.

6. Either 40H or 10H is recognized by the WSM as the

WA = Address of memory location to be written.

byte write setup.

3. SRD = Data read from status register. See Table 13.1

7. A block lock-bit can be set while WP# is VIH.

for a description of the status register bits.

8. WP# must be at VIH to clear block lock-bits. The clear

WD = Data to be written at location WA. Data is latched

block lock-bits operation simultaneously clears all block

on the rising edge of WE# or CE# (whichever

lock-bits.

goes high first).

9. Following the Third Bus Cycle, inputs the write address

ID = Data read from identifier codes.

and write data of "N" times. Finally, input the confirm

QD = Data read from query database.

command "D0H".

4. Following the Read Identifier Codes command, read

10. Commands other than those shown above are reserved

operations access manufacture, device and block status

by SHARP for future device implementations and should

codes. See Section 4.2 for read identifier code data.

not be used.

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