LH28F160S5HB-L70 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F160S5HB-L70

16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)

Sharp Electronics 

4.1 Read Array Command

Upon initial device power-up and after exit from

deep power-down mode, the device defaults to

read array mode. This operation is also initiated by

writing the Read Array command. The device

remains enabled for reads until another command

is written. Once the internal WSM has started a

block erase, full chip erase, (multi) word/byte write

or block lock-bit configuration, the device will not

recognize the Read Array command until the WSM

completes its operation unless the WSM is

suspended via an Erase Suspend and (Multi)

Word/Byte Write Suspend command. The Read

Array command functions independently of the VPP

voltage and RP# must be VIH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing

the Read Identifier Codes command. Following the

command write, read cycles from addresses shown

in Fig. 2 retrieve the manufacture, device, block

lock configuration and block erase status (see

Table 4 for identifier code values). To terminate the

operation, write another valid command. Like the

Read Array command, the Read Identifier Codes

command functions independently of the VPP

voltage and RP# must be VIH. Following the Read

Identifier Codes command, the following information

can be read :

Table 4 Identifier Codes

CODE

ADDRESS DATA

Manufacture Code

00000H

B0

00001H

Device Code

Block Status Code

00002H

D0

00003H

X0004H (NOTE 1)

X0005H (NOTE 1)

• Block is Unlocked

DQ0 = 0

• Block is Locked

DQ0 = 1

• Last erase operation

completed successfully

DQ1 = 0

• Last erase operation did

not completed successfully

DQ1 = 1

• Reserved for Future Use

DQ2-7

LH28F160S5-L/S5H-L

NOTE :

1. X selects the specific block status code to be read. See

Fig. 2 for the device identifier code memory map.

4.3 Read Status Register Command

The status register may be read to determine when

a block erase, full chip erase, (multi) word/byte

write or block lock-bit configuration is complete and

whether the operation completed successfully (see

Table 13.1). It may be read at any time by writing

the Read Status Register command. After writing

this command, all subsequent read operations

output data from the status register until another

valid command is written. The status register

contents are latched on the falling edge of OE# or

CE# (Either CE0# or CE1#), whichever occurs. OE#

or CE# (Either CE0# or CE1#) must toggle to VIH

before further reads to update the status register

latch. The Read Status Register command

functions independently of the VPP voltage. RP#

must be VIH.

The extended status register may be read to

determine multi byte write availability (see Table

13.2). The extended status register may be read at

any time by writing the Multi Byte Write command.

After writing this command, all subsequent read

operations output data from the extended status

register, until another valid command is written. The

contents of the extended status register are latched

on the falling edge of OE# or CE# (Either CE0# or

CE1#), whichever occurs last in the read cycle.

Multi Byte Write command must be re-issued to

update the extended status register latch.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 and SR.1 are

set to "1"s by the WSM and can only be reset by

the Clear Status Register command. These bits

indicate various failure conditions (see Table 13.1).

By allowing system software to reset these bits,

several operations (such as cumulatively erasing or

locking multiple blocks or writing several bytes in

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