PIC17LC752-08/JWQTP View Datasheet(PDF) - Microchip Technology

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Description

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PIC17LC752-08/JWQTP

High-Performance 8-Bit CMOS EPROM Microcontrollers

Microchip Technology 

15.2.13 CLOCK ARBITRATION

Clock arbitration occurs when the master during any

receive, transmit, or restart/stop condition de-asserts

the SCL pin (SCL allowed to float high). When the

SCL pin is allowed to float high, the baud rate genera-

tor (BRG) is suspended from counting until the SCL

pin is actually sampled high. When the SCL pin is

sampled high, the baud rate generator is reloaded with

the contents of SSPADD<6:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count in the event that the

clock is held low by an external device. (Figure 15-36)

PIC17C75X

FIGURE 15-36: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE

BRG overflow,

Release SCL,

If SCL = 1 Load BRG with

SSPADD<6:0>, and start count

to measure high time interval

BRG overflow occurs,

Release SCL, Slave device holds SCL low.

SCL = 1 BRG starts counting

clock high interval.

SCL

SCL line sampled once every machine cycle (Tosc • 4).

Hold off BRG until SCL is sampled high.

SDA

TBRG

TBRG

TBRG

© 1997 Microchip Technology Inc.

Preliminary

DS30264A-page 159

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