PIC17LC752-08/JWQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC17LC752-08/JWQTP

High-Performance 8-Bit CMOS EPROM Microcontrollers

Microchip Technology 

PIC17C75X

FIGURE F-5: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)

R-0

PEIF

bit7

bit 7:

R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0

T0CKIF T0IF INTF

PEIE T0CKIE T0IE

INTE

bit0

R = Readable bit

W = Writable bit

- n = Value at POR reset

PEIF: Peripheral Interrupt Flag bit

This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.

1 = A peripheral interrupt is pending

0 = No peripheral interrupt is pending

bit 6:

T0CKIF: External Interrupt on T0CKI Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h).

1 = The software specified edge occurred on the RA1/T0CKI pin

0 = The software specified edge did not occur on the RA1/T0CKI pin

bit 5:

T0IF: TMR0 Overflow Interrupt Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h).

1 = TMR0 overflowed

0 = TMR0 did not overflow

bit 4:

INTF: External Interrupt on INT Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h).

1 = The software specified edge occurred on the RA0/INT pin

0 = The software specified edge did not occur on the RA0/INT pin

bit 3:

PEIE: Peripheral Interrupt Enable bit

This bit enables all peripheral interrupts that have their corresponding enable bits set.

1 = Enable peripheral interrupts

0 = Disable peripheral interrupts

bit 2:

T0CKIE: External Interrupt on T0CKI Pin Enable bit

1 = Enable software specified edge interrupt on the RA1/T0CKI pin

0 = Disable interrupt on the RA1/T0CKI pin

bit 1:

T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enable TMR0 overflow interrupt

0 = Disable TMR0 overflow interrupt

bit 0:

INTE: External Interrupt on RA0/INT Pin Enable bit

1 = Enable software specified edge interrupt on the RA0/INT pin

0 = Disable software specified edge interrupt on the RA0/INT pin

© 1997 Microchip Technology Inc.

Preliminary

DS30264A-page 277

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