PIC18F8520-IPT301 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F8520-IPT301

64/80-Pin High-Performance, 256 Kbit to 1 MbitEnhanced Flash Microcontrollers with A/D

Microchip Technology 

PIC18F6520/8520/6620/8620/6720/8720

CPFSGT

Compare f with W, skip if f > W

Syntax:

[ label ] CPFSGT f [,a]

Operands:

0  f  255

a  [0,1]

Operation:

(f) W),

skip if (f) > (W)

(unsigned comparison)

Status Affected: None

Encoding:

0110 010a ffff ffff

Description:

Compares the contents of data

memory location ‘f’ to the contents

of W by performing an unsigned

subtraction.

If the contents of ‘f’ are greater than

the contents of WREG, then the

fetched instruction is discarded and

a NOP is executed instead, making

this a two-cycle instruction. If ‘a’ is

‘0’, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Words:

1

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Decode

Read

register ‘f’

If skip:

Q1

Q2

Q3

Process

Data

Q3

Q4

No

operation

Q4

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

No

operation

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

Example:

HERE

CPFSGT REG, 0

NGREATER :

GREATER :

Before Instruction

PC

=

W

=

Address (HERE)

?

After Instruction

If REG



PC

=

If REG



PC

=

W;

Address (GREATER)

W;

Address (NGREATER)

CPFSLT

Compare f with W, skip if f < W

Syntax:

[ label ] CPFSLT f [,a]

Operands:

0  f  255

a  [0,1]

Operation:

(f) –W),

skip if (f) < (W)

(unsigned comparison)

Status Affected: None

Encoding:

0110 000a ffff ffff

Description:

Compares the contents of data

memory location ‘f’ to the contents

of W by performing an unsigned

subtraction.

If the contents of ‘f’ are less than

the contents of W, then the fetched

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction. If ‘a’ is ‘0’, the

Access Bank will be selected. If ‘a’

is ‘1’, the BSR will not be

overridden (default).

Words:

1

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

No

operation

If skip:

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

Example:

HERE

NLESS

LESS

CPFSLT REG, 1

:

:

Before Instruction

PC

=

W

=

After Instruction

If REG

<

PC

=

If REG



PC

=

Address (HERE)

?

W;

Address (LESS)

W;

Address (NLESS)

 2003-2013 Microchip Technology Inc.

DS39609C-page 277

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