PIC18F8520-IPT301 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F8520-IPT301

64/80-Pin High-Performance, 256 Kbit to 1 MbitEnhanced Flash Microcontrollers with A/D

Microchip Technology 

PIC18F6520/8520/6620/8620/6720/8720

INCFSZ

Increment f, skip if 0

Syntax:

[ label ] INCFSZ f [,d [,a]

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(f) + 1  dest,

skip if result = 0

Status Affected: None

Encoding:

0011 11da ffff ffff

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result

is placed back in register ‘f’

(default).

If the result is ‘0’, the next

instruction which is already fetched

is discarded and a NOP is executed

instead, making it a two-cycle

instruction. If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Words:

1

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Decode

Read

register ‘f’

If skip:

Q1

Q2

Q3

Process

Data

Q4

Write to

destination

Q3

Q4

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

No

operation

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

Example:

HERE

NZERO

ZERO

INCFSZ

:

:

CNT, 1, 0

Before Instruction

PC

= Address (HERE)

After Instruction

CNT = CNT + 1

If CNT = 0;

PC

= Address (ZERO)

If CNT  0;

PC

= Address (NZERO)

INFSNZ

Increment f, skip if not 0

Syntax:

[ label ] INFSNZ f [,d [,a]

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(f) + 1  dest,

skip if result  0

Status Affected: None

Encoding:

0100 10da ffff ffff

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result

is placed back in register ‘f’

(default).

If the result is not ‘0’, the next

instruction which is already fetched

is discarded and a NOP is executed

instead, making it a two-cycle

instruction. If ‘a’ is ‘0’, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Words:

1

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Decode

Read

register ‘f’

If skip:

Q1

Q2

Q3

Process

Data

Q4

Write to

destination

Q3

Q4

No

operation

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

Example:

HERE

ZERO

NZERO

INFSNZ REG, 1, 0

Before Instruction

PC

= Address (HERE)

After Instruction

REG = REG + 1

If REG  0;

PC

= Address (NZERO)

If REG = 0;

PC

= Address (ZERO)

 2003-2013 Microchip Technology Inc.

DS39609C-page 281

Share Link: