PIC18LF8520-IPT301 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF8520-IPT301

64/80-Pin High-Performance, 256 Kbit to 1 MbitEnhanced Flash Microcontrollers with A/D

Microchip Technology 

PIC18F6520/8520/6620/8620/6720/8720

TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on Details

POR, BOR on page:

PREINC2

PLUSW2

FSR2H

FSR2L

STATUS

TMR0H

TMR0L

T0CON

OSCCON

LVDCON

WDTCON

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented

(not a physical register)

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented

(not a physical register) – value of FSR2 offset by value in WREG

—

—

—

—

Indirect Data Memory Address Pointer 2 High Byte

Indirect Data Memory Address Pointer 2 Low Byte

—

—

—

N

OV

Z

DC

C

Timer0 Register High Byte

Timer0 Register Low Byte

TMR0ON T08BIT

T0CS

T0SE

PSA

T0PS2

T0PS1

T0PS0

—

—

—

—

—

—

—

SCS

—

—

IRVST

LVDEN

LVDL3

LVDL2

LVDL1

LVDL0

—

—

—

—

—

—

—

SWDTE

n/a

57

n/a

57

---- 0000 33, 57

xxxx xxxx 33, 57

---x xxxx 33, 59

0000 0000 33, 133

xxxx xxxx 33, 133

1111 1111 33, 131

---- ---0 25, 33

--00 0101 33, 235

---- ---0 33, 250

RCON

IPEN

—

—

RI

TO

PD

POR

BOR 0--1 11qq 33, 60,

101

TMR1H Timer1 Register High Byte

xxxx xxxx 33, 135

TMR1L

Timer1 Register Low Byte

xxxx xxxx 33, 135

T1CON

TMR2

PR2

T2CON

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

RD16

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 33, 135

Timer2 Register

0000 0000 33, 141

Timer2 Period Register

1111 1111 33, 142

—

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 33, 141

SSP Receive Buffer/Transmit Register

SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode.

xxxx xxxx 33, 157

0000 0000 33, 166

SMP

CKE

D/A

P

S

R/W

UA

BF 0000 0000 33, 158

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1 SSPM0 0000 0000 33, 168

GCEN ACKSTAT ACKDT

ACKEN

RCEN

PEN

RSEN

SEN 0000 0000 33, 169

A/D Result Register High Byte

xxxx xxxx 34, 215

A/D Result Register Low Byte

xxxx xxxx 34, 215

ADCON0

—

—

CHS3

CHS2

CHS1

CHS0 GO/DONE ADON --00 0000 34, 213

ADCON1

—

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1 PCFG0 --00 0000 34, 214

ADCON2

ADFM

—

—

—

—

ADCS2

ADCS1 ADCS0 0--- -000 34, 215

CCPR1H Capture/Compare/PWM Register 1 High Byte

xxxx xxxx 34, 151,

152

CCPR1L Capture/Compare/PWM Register 1 Low Byte

xxxx xxxx 34, 151,

152

CCP1CON

—

—

DC1B1

DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 34, 149

CCPR2H Capture/Compare/PWM Register 2 High Byte

xxxx xxxx 34, 151,

152

CCPR2L Capture/Compare/PWM Register 2 Low Byte

xxxx xxxx 34, 151,

152

CCP2CON

—

—

DC2B1

DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 34, 149

Legend:

Note 1:

2:

3:

x = unknown, u = unchanged, – = unimplemented, q = value depends on condition

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator

modes.

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X20 devices; always maintain these clear.

 2003-2013 Microchip Technology Inc.

DS39609C-page 53

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