PSD913G3V-B-90UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD913G3V-B-90UI Datasheet PDF : 94 Pages
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PSD9XX Family
Preliminary Information
Microcontroller Interface – PSD9XXFV AC/DC Parameters
(3 V Versions)
Write Timing (3 V Versions)
-12
-15
Symbol
Parameter
Conditions Min Max Min Max
t LVLX
t AVLX
t LXAX
t AVWL
t SLWL
t DVWH
t WHDX
t WLWH
t WHAX1
t WHAX2
t WHPV
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Input Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
26
26
(Note 1)
9
10
(Note 1)
9
12
(Notes 1 and 3) 17
20
(Note 3)
17
20
(Note 3)
45
45
(Note 3)
7
8
(Note 3)
46
48
(Note 3)
10
12
(Notes 3 and 4) 0
0
(Note 3)
33
35
t AVPV
Address Input Valid to Address
Output Delay
(Note 2)
33
35
NOTES: 1. Any input used to select an internal PSD813F function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
-20
Min Max
30
12
14
25
25
50
10
53
17
0
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLD Combinatorial Timing (3 V Versions)
Symbol
t PD
t ARD
Parameter
PLD Input Pin/Feedback
to PLD Combinatorial
Output
PLD Array Delay
-12
-15
-20
Conditions Min Max Min Max Min Max
40
45
50
Any
25
Micro⇔Cell
29
33
Fast
Slew
PT TURBO Rate
Aloc OFF (Note 1) Unit
Add 4 Add 20 Sub 6 ns
Add 4
ns
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
74
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