ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
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ST10F269Z2QX Datasheet PDF : 161 Pages
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ST10F269Z2Qx
Table 36 : Demultiplexed Bus Characteristics
Symbol
Parameter
Maximum CPU Clock
= 40MHz
Minimum Maximum
Variable CPU Clock
1/2 TCL = 1 to 40MHz
Minimum
Maximum
t41 CC Latched CS hold after RD, WR
t82 CC Address setup to RdCS, WrCS
(with RW-delay)
t83 CC Address setup to RdCS, WrCS
(no RW-delay)
t46 SR RdCS to Valid Data In
(with RW-delay)
t47 SR RdCS to Valid Data In
(no RW-delay)
t48 CC RdCS, WrCS Low Time
(with RW-delay)
t49 CC RdCS, WrCS Low Time
(no RW-delay)
t50 CC Data valid to WrCS
t51 SR Data hold after RdCS
t53 SR Data float after RdCS
(with RW-delay)
3
2 + tF
14.5 + 2tA
2 + 2tA
–
–
15.5 + tC
28 + tC
10 + tC
0
–
–
TCL - 10.5 + tF
–
ns
–
2 TCL - 10.5 +
–
ns
2tA
–
TCL - 10.5 + 2tA
–
ns
4 + tC
–
2 TCL - 21 + tC ns
16.5 + tC
–
3 TCL - 21 + tC ns
–
2 TCL - 9.5
+ tC
–
ns
–
3 TCL - 9.5 + tC
–
ns
–
–
16.5 + tF
2 TCL - 15 + tC
–
ns
0
–
ns
–
2 TCL - 8.5 + tF ns
t68 SR Data float after RdCS
–
(no RW-delay)
3
4 + tF
–
TCL - 8.5 + tF ns
t55 CC Address hold after
RdCS, WrCS
-8.5 + tF
–
-8.5 + tF
–
ns
t57 CC Data hold after WrCS
2 + tF
–
TCL - 10.5 + tF
–
ns
Notes: 1. RW-delay and tA refer to the next following bus cycle.
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
148/161
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