ST10F269Z2Qx
The structure of Port 7 differs in the way the output
latches are connected to the internal bus and to
the pin driver. Pins P7.3...P7.0 (POUT3...POUT0)
EXOR the alternate data output with the port latch
output, which allows to use the alternate data
directly or inverted at the pin driver.
Figure 40 : Block Diagram of Port 7 Pins P7.3...P7.0
Write ODP7.y
Open Drain
Latch
Read ODP7.y
Write DP7.y
Direction
Latch
Read DP7.y
Write DP7.y
Port Output
Latch
Read P7.y
Alternate
Data
Output
Port Data
Output
=1
EXOR
1
MUX
0
Output
Buffer
Clock
Input
Latch
P7.y/POUTy
y = 0...3
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