ST10F269Z2Qx
The structure of Port 8 differs in the way the
output latches are connected to the internal bus
and to the pin driver (see Figure 43). Pins
P8.7...P8.0 (CC23IO...CC16IO) combine internal
bus data and alternate data output before the port
latch input, as do the Port 2 pins.
Figure 43 : Block Diagram of Port 8 Pins P8.7...P8.0
Write ODP8.y
Open Drain
Latch
Read ODP8.y
Write DP8.y
Direction
Latch
Read DP8.y
Alternate
Data
Output
1
MUX
0
Write Port P8.y
Compare Trigger
Read P8.y
Output
Latch
Output
Buffer
P8.y
CCzIO
≥1
1
MUX
0
Alternate Latch
Data Input
Clock
Input
Latch
Alternate Pin
Data Input
y = (7...0)
z = (16...23)
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