Memory
code
2FF0
2FF2
2FF4
62F4
2FF1
2FF3
2FF5
Mnemonic
devlb
devls
devlw
devmove
devsb
devss
devsw
Processor Name
cycles
3
device load byte
3
device load sixteen
3
device load word
device move
3
device store byte
3
device store sixteen
3
device store word
Table 6.19 Device access instructions
Memory
code
Mnemonic
Processor Name
cycles
60F5
60F4
wait
signal
4 to 10
6 to 10
wait
signal
Table 6.20 Semaphore instructions
Memory
code
60F0
60F1
60F2
60F3
60FC
60FD
62FE
62FF
61FF
2BF0
2CF4
2CF5
2CFD
2CFE
Mnemonic
Processor Name
cycles
swapqueue
3
swap scheduler queue
swaptimer
5
swap timer queue
insertqueue
1 to 2 insert at front of scheduler queue
timeslice
3 to 4 timeslice
ldshadow
6 to 23 load shadow registers
stshadow
5 to 17 store shadow registers
restart
19
restart
causeerror
2
cause error
iret
3 to 9 interrupt return
settimeslice
1
set timeslicing status
intdis
1
interrupt disable
intenb
2
interrupt enable
gintdis
2
global interrupt disable
gintenb
2
global interrupt enable
Table 6.21 Scheduling support instructions
ST20-GP1
Notes
A
A
A
I
A
A
A
Notes
D
Notes
A
A
43/116
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