ST20-GP1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST20-GP1

GPS PROCESSOR

STMicroelectronics 

ST20-GP1

7 Memory map

The ST20-GP1 processor memory has a 32-bit signed address range. Words are addressed by

30-bit word addresses and a 2-bit byte-selector identifies the bytes in the word. Memory is divided

into 4 banks which can each have different memory characteristics and can be used for different

purposes. In addition, on-chip peripherals can be accessed via the device access instructions (see

Table 6.19).

Various memory locations at the bottom and top of memory are reserved for special system

purposes. There is also a default allocation of memory banks to different uses.

Note that the ST20-GP1 uses 30 bits of addressing internally, but addresses A20-A29 are not

brought out to external pins. Address bits A30 and A31 are used as bank selects.

7.1 System memory use

The ST20-GP1 has a signed address space where the address ranges from MinInt (#80000000)

at the bottom to MaxInt (#7FFFFFFF) at the top. The ST20-GP1 has an area of 4 Kbytes of RAM

at the bottom of the address space provided by on chip memory. The bottom of this area is used to

store various items of system state. These addresses should not be accessed directly but via the

appropriate instructions.

Near the bottom of the address space there is a special address MemStart. Memory above this

address is for use by user programs while addresses below it are for private use by the processor

and used for subsystem channels and trap handlers. The address of MemStart can be obtained

via the ldmemstartval instruction.

7.1.1 Subsystem channels memory

Each DMA channel between the processor and a subsystem is allocated a word of storage below

MemStart. This is used by the processor to store information about the state of the channel. This

information should not normally be examined directly, although debugging kernels may need to do

so.

Boot channel

The subsystem channel which is a link input channel is identified as a ‘boot channel’. When the

processor is reset, and is set to boot from link, it waits for boot commands on this channel.

7.1.2 Trap handlers memory

The area of memory reserved for trap handlers is broken down hierarchically. Full details on trap

handlers is given in see Section 4.6 on page 23.

• Each high/low process priority has a set of trap handlers.

• Each set of trap handlers has a handler for each of the four trap groups (refer to Section

4.6.1).

• Each trap group handler has a trap handler structure and a trapped process structure.

• Each of the structures contains four words, as detailed in Section 4.6.3.

The contents of these addresses can be accessed via ldtraph, sttraph, ldtrapped and sttrapped

instructions.

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