ST20-GP1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST20-GP1 Datasheet PDF : 116 Pages
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ST20-GP1
PlinkEmi register
The PlinkEmi register determines the mode of operation of the port.
PlinkEmi
Bit
Bit field
0
PlinkEmi
Parallel port base address + #00
Function
This bit determines the mode of operation of the port.
PlinkEmi
Mode
0
DMA mode (reset state)
1
EMI mode
Table 15.1 PlinkEmi register format
Read/Write
PlinkIO
The PlinkIO register determines the direction of the port interactions when in the DMA mode of
operation.
PlinkIO
Parallel port base address + #04
Read/Write
Bit
Bit field
0
PlinkIO
Function
This bit controls the direction of the parallel port interactions when in DMA mode.
PlinkIO
Direction
0
inputs (reset state)
1
outputs
Table 15.2 PlinkIO register format
PlinkMode
The PlinkMode register determines the external protocol used for interactions.
PlinkMode
Bit
Bit field
0
PlinkMode
Parallel port base address + #08
Function
These bits control the external protocol used for interactions.
PlinkMode Protocol
00
Idle (reset state)
01
Dreq/Dack mode
10
Valid/Ack mode
11
Direct mode
Table 15.3 PlinkMode register format
Read/Write
15.4 External data transfer protocols
The byte-wide parallel port has three control pins. PlinknotReq and PlinknotAck control data
transfers and the PlinkOut pin controls external buffers, if required (e.g. an external 3V/5V buffer
device). When the PlinkOut pin is high it signals the plink is outputting.
The control pins can support three external protocols, as follows:
• Dreq/Dack protocol
• Valid/Ack protocol
• Direct DMA protocol
The protocol used for interactions is programmable via the PlinkMode register. In addition, the
direction of the link is controlled by the PlinkIO register (see Table 15.2).
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