ST72E311J4D0S View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72E311J4D0S

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

ST72E311 ST72T311

PERIPHERAL CHARACTERISTICS (Cont’d)

(TA = -40°C to +125°C and VDD = 5V±10% unless otherwise specified )

A/D Converter Specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TSAMPLE Sample Duration

Res

ADC Resolution

DLE

Differential Linearity Error*

fCPU=8MHz

VDD=VDDA=5V

31.5

8

±0.6

1/fCPU

bit

±1

ILE

Integral Linearity Error*

±2

VAIN

IADC

tSTAB

tCONV

RAIN

CHOLD

RSS

Analog Input Voltage

Supply current rise

during A/D conversion

Stabilization time after ADC enable

Conversion Time

fCPU=8MHz

VDD=VDDA=5V

Resistance of analog sources

(VAIN)

Hold Capacitance

Resistance of sampling switch and

internal trace

fCPU=8MHz, T=25°C,

VDD=VDDA=5V

VSSA

VDDA V

1

mA

30

µs

8

µs

64

1/fCPU

15

ΚΩ

22

pF

2

ΚΩ

*Note: ADC Accuracy vs. Negative Injection Current:

For Iinj-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is

a loss of 1 LSB by 10KΩ increase of the external analog source impedance.

These measurements results and recommendations take worst case injection conditions into account:

- negative injection

- injection to an Input with analog capability, adjacent to the enabled Analog Input

- at 5V VDD supply, and worst case temperature.

VAIN

RAIN

Px.x/AINx

Cpin

Cpin = input capacitance

5pF

VT

= threshold voltage

SS

= sampling switch

Chold = sample/hold

capacitance

leakage = leakage current

at the pin due

to various junctions

VDD

VT = 0.6V

Sampling

Switch

SS

RSS

2ΚΩ

VT = 0.6V

leakage max.

±1µA

Chold

22 pF

VSS

91/101

91

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