STULPI01A - STULPI01B
ULPI registers
Table 20. USB interrupt enable rising register
0Dh-0Fh(Read), 0Dh(Write), 0Eh(Set), 0Fh(Clear)
(If set, the bits in this register cause an interrupt event notification to be generated when the
corresponding PHY signal changes from low to high. By default, all transitions are enabled. RxActive and
RxError must always be communicated immediately and so are not included in this register. Interrupt
circuitry can be powered down in any mode when both rising and falling edge enables are disabled. To
ensure interrupts are detectable when clock is powered down, the link should enable both rising and
falling edges.)
Field name
Bits Access Reset
Description
Host disconnect rise
VbusValid rise
0
rd/wr/s/c
1
rd/wr/s/c
Generates an interrupt event notification when host
1b
disconnect changes from low to high. Applicable only in
host mode (DpPulldown and DmPulldown both set to
1b).
1b
Generates an interrupt event notification when
VbusValid changes from low to high.
SessValid rise
SessEnd rise
2
rd/wr/s/c
3
rd/wr/s/c
Generate an interrupt event notification when SessValid
1b changes from low to high. SessValid is the same as
UTMI+ Avalid.
1b
Generates an interrupt event notification when SessEnd
changes from low to high.
ID rise
4
rd/wr/s/c
Generates an interrupt event notification when ID
1b
changes from low to high. ID is valid 50ms after IdPullup
is set to 1b, otherwise ID is undefined and should be
ignored.
Reserved
7:5 rd/wr/s/c
0b Reserved.
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