STULPI01ATBR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STULPI01ATBR Datasheet PDF : 44 Pages
| |||
STULPI01A - STULPI01B
ULPI registers
Table 23. USB interrupt latch register
Address: 14h (Read-only with auto clear)
(These bits are set by the STULPI01 when an unmasked change occurs on the corresponding internal
signal. The STULPI01 will automatically clear all bits when the link reads this register, or when low power
mode is entered. The STULPI01 also clears this register when serial mode or car kit mode is entered
regardless of the value of ClockSuspendM. The interrupt circuitry is powered down in any mode when
both rising and falling edge enables are disabled. To ensure the interrupts are detectable when the clock
is powered down, the link should enable both rising and falling edges.
The STULPI01 follows the rules in Table 20 for setting any latch register bit. It is important to note that if
the register read data is returned to the Link in the same cycle that a USB interrupt latch bit is to be set,
the interrupt condition is given immediately in the register read data and the latch bit is not set.
Note that it is optional for the link to read the USB interrupt latch register in synchronous mode because
the RX CMD byte already indicates the interrupt source directly.)
Field name
Bits Access Reset
Description
Host disconnect
latch
0
rd
VbusValid latch
1
rd
SessValid latch
2
rd
SessEnd latch
3
rd
ID latch
4
rd
Set to 1b by the STULPI01 when an unmasked event
0b occurs on host disconnect. Cleared when this register is
read. Applicable only in host mode.
0b
Set to 1b by the STULPI01 when an unmasked event
occurs on VbusValid. Cleared when this register is read.
Set to 1b by the STULPI01 when an unmasked event
0b occurs on SessValid. Cleared when this register is read.
SessValid is the same as UTMI+Avalid.
0b
Set to 1b by the STULPI01 when an unmasked event
occurs on SessEnd. Cleared when this register is read.
Set to 1b by the STULPI01 when an unmasked event
0b
occurs on ID. Cleared when this register is read. ID is valid
50ms after ID is set to 1b, otherwise ID is undefined and
should be ignored.
Reserved
7:5
rd
0b Reserved
Table 24. Setting rules for interrupt latch register
Input conditions
Register read data returned in
current clock cycle
Interrupt latch bit is to be set in
current clock cycle
No
No
No
Yes
Yes
No
Yes
Yes
Resultant value of latch register bit
0
1
0
0
37/44
Share Link: 