PIC16F/LF1826/27
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 5
280h(2) INDF0
281h(2) INDF1
282h(2)
283h(2)
284h(2)
285h(2)
286h(2)
287h(2)
288h(2)
289h(2)
28Ah(2)
28Bh(2)
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
DC
BSR1
INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
BSR0
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
28Ch —
Unimplemented
—
—
28Dh —
Unimplemented
—
—
28Eh —
Unimplemented
—
—
28Fh
—
Unimplemented
—
—
290h
—
Unimplemented
—
—
291h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
292h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
293h
CCP1CON
P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
294h
PWM1CON
P1RSEN
P1DC6
P1DC5
P1DC4
P1DC3
P1DC2 P1DC1 P1DC0 0000 0000 0000 0000
295h
CCP1AS
CCP1ASE CCP1AS2 CCP1AS1 CCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000
296h
PSTR1CON
—
—
—
STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
—
Unimplemented
CCPR2L(1) Capture/Compare/PWM Register 2 (LSB)
CCPR2H(1) Capture/Compare/PWM Register 2 (MSB)
CCP2CON(1)
P2M1
P2M0
DC2B1
DC2B0
PWM2CON(1) P2RSEN
P2DC6
P2DC5
P2DC4
CCP2AS(1) CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0
PSTR2CON(1)
—
—
—
STR2SYNC
CCPTMRS(1) C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0
CCP2M3
P2DC3
PSS2AC1
STR2D
C2TSEL1
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000
P2DC2 P2DC1 P2DC0 0000 0000 0000 0000
PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000
STR2C STR2B STR2A ---0 0001 ---0 0001
C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
29Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F/LF1827 only.
These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 35