STA333ML View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STA333ML

2-channel microless high-efficiency digital audio system Sound Terminal ®

STMicroelectronics 

Electrical specifications

3.6

Power-on sequence

Figure 3. Power-on sequence

STA333ML

3.7

VCC

VDD_Dig

Don’t care

XTI

Reset

Don’t care

TR

PWDN

TR = minimum time between XTI master clock stable and reset removal: 1 ms

Note 1: clock stable means: fmax - fmin < 1 MHz

Note 2: No specific VCC and VDD turn-on sequence is required.

Test circuits

Figure 4. Resistive load

OUTxY

Vcc

Low current dead time = MAX(DTr,DTf)

Duty cycle = 50%

INxY

+Vcc

M58

OUTxY

M57

gnd

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

t

DTr

DTf

R 8Ω

+

-

V67 =

vdc = Vcc/2

D03AU1458

Duty cycle=A

DTin(A)

INA

Figure 5. Test circuit

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

+VCC

DTout(A)

M58

Q1

Q2

M64

OUTA

Rload=8Ω

DTout(B)

OUTB

L67 22µ

Iout=4A

L68 22µ

Iout=4A

M57

Q3Lout = 1.5 A

C69

470nF

C71 470nF

C70

Q4

470nF Lout = 1.5 A

M63

Duty cycle=B

DTin(B)

INB

Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure

D03AU1517

10/23

DocID13177 Rev 8

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