STE2002(2002) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STE2002
(Rev.:2002)

81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STMicroelectronics 

STE2002

ELECTRICAL CHARACTERISTICS

AC OPERATION

(VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11V; Tamb =-40 to 85°C; unless otherwise specified)

Symbol

Parameter

Test Condition

Min. Typ. Max. Unit

I2C BUS INTERFACE (See note 4)

FSCL SCL Clock Frequency

Fast Mode

DC

400

kHz

High Speed Mode; Cb=100pF

DC

(max);VDD1=2

3.4

MHz

High Speed Mode; Cb=400pF

DC

(max); VDD1=2

1.7

MHz

Fast Mode; VDD1=1.7V

400 KHz

TSU;STA Set-up time (repeated) START Note 2, 3, Cb=100pF

160

ns

condition

THD;STA Hold time (repeated) START

Note 2, 3, Cb=100pF

160

ns

condition

TLOW LOW period of the SCLH clock Note 2, 3, Cb=100pF

160

ns

THIGH HIGH period of the SCLH clock Note 2, 3, Cb=100pF

60

ns

TSU;DAT Data set-up time

Note 2, 3, Cb=100pF

10

ns

THD;DAT Data hold time

Note 2, 3; Cb=100pF

40

ns

Tr;CL Rise time of SCLH signal

Note 2, 3; Cb=100pF

10

ns

TrCL1 Rise time of SCLH signal after a Note 2, 3, Cb=100pF

10

ns

repeated START condition and

after an acknowledge bit

TfCL Fall time of SCLH signal

Note 2, 3, Cb=100pF

10

ns

TrDA Rise time of SDAH signal

Note 2, 3, 4, Cb=100pF

10

ns

TfDA Fall time of SDAH signal

Note 2, 3, 4, Cb=100pF

10

80

ns

TrDA Rise time of SDAH signal

Note 2, 3, 4, Cb=400pF

20

ns

TfDA Fall time of SDAH signal

Note 2, 3, 4, Cb=400pF

20

160

ns

TSU;STO Set-up time for STOP condition Note 2, 3, Cb=100pF

160

ns

Cb Capacitive load for SDAH and

SCLH

100

400

pF

Cb Capacitive load for SDAH + SDA

line and SCLH + SCL line

400

pF

Figure 49. I2C-bus timings

Sr

tfDA

trDA

Sr P

SDAH

tSU;STA

tHD;DAT

tHD;STA

tSU;DAT

SCLH

tfCL

trCL

= MCS current source pull-up

= Rp resistor pull-up

tHIGH tLOW

trCL1

(1)

tLOW tHIGH

trCL1

(1)

D00IN1153

41/51

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