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STM8S105C2P6TR View Datasheet(PDF) - STMicroelectronics

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STM8S105C2P6TR Datasheet PDF : 56 Pages
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STM8S103xx, STM8S105xx
Electrical characteristics
7.3.1 I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 14. I/O static characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level
voltage
-0.3 V
TBD
V
VIH
Input high level
voltage
VDD = 5.0 V
0.7 x VDD
VDD + 0.3 V
V
Vhys Hysteresis(2)
700
mV
Rpu Pull-up resistor
VDD = 5 V, VIN=VSS
30
45
60
kΩ
tR, tF
Rise and fall time
(10% - 90%)
Fast I/Os
Load = 50 pF
Standard and high sink I/Os
Load = 50 pF
20 (3)
ns
125 (3)
ns
Input leakage
Ilkg current,
VSS≤VIN≤VDD
analog and digital
±1 (3)
µA
Ilkg ana
Analog input
leakage current
VSS≤VIN≤VDD
±250 (3)
nA
Ilkg(inj)
Leakage current in
adjacent I/O(3)
Injection current ±4 mA
±1(3)
µA
1. TBD = to be determined.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
3. Data based on characterization results, not tested in production.
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