Z8F041APJ020EG View Datasheet(PDF) - Zilog
Part Name
Description
Manufacturer
Z8F041APJ020EG Datasheet PDF : 282 Pages
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Z8 Encore! XP® F082A Series
Product Specification
244
Figure 38 and Table 147 provide timing information for UART pins for the case where
CTS is not used for flow control. DE asserts after the Transmit Data Register has been
written. DE remains asserted for multiple characters as long as the Transmit Data Register
is written with the next character before the current character has completed.
T2
DE
(Output)
TXD
(Output)
start bit0
bit 1
T1
bit 7 parity stop
end of
stop bit(s)
Figure 38. UART Timing Without CTS
Table 147. UART Timing Without CTS
Parameter Abbreviation
UART
T1
T2
DE assertion to TXD falling edge (start bit) delay
End of Stop Bit(s) to DE deassertion delay (Tx
Data Register is empty)
Delay (ns)
Minimum
Maximum
1 * XIN period
±5
1 bit time
PS022827-1212
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
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