LT3669EUFD View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LT3669EUFD

IO-Link Transceiver with Integrated Step-Down Regulator and LDO

Linear Technology 

LT3669/LT3669-2

APPLICATIONS INFORMATION

If the junction temperature exceeds 140°C (typical), internal

circuitry will shut the line drivers off. During the thermal

shutdown event, SC1 and SC2 pull low simultaneously

regardless of the level of the enable inputs TXEN1 and

TXEN2 (see Figure 13). This behavior can be used to

distinguish between short-circuit and thermal shutdown

events. In case of short-circuit events without thermal

shutdown being triggered, setting TXEN1 and TXEN2 low

sets outputs SC1 and SC2 to high impedance, respectively.

While in short-circuit, the line drivers will pulse follow-

ing the pulsing scheme described earlier. Depending on

the cable length and nature of the heavy load, outputs

SC1 and SC2 may report false information as the voltage

across the line drivers exceeds the short-circuit range for

a short time due to reflections in the cable at the begin-

ning of each pulse. SC1 and SC2 should then be filtered

digitally or by an RC filter before further processing. The

analog filter should have a time constant of at least 80µs,

for example, using pull-up resistors of 100k for SC1 and

SC2 with 1nF to ground.

Driving Heavy Loads on Q2 During CQ1

Communication

The line drivers enter the protecting pulsing mechanism

independently from each other. Only the driver under heavy

load conditions will shut off after the defined pulsing on-

time. While this driver is under overload conditions data

can be sent reliably on the other driver in COM2 (SR <

0.4V) provided that it is enabled a minimum of 3ms before

the data is actually applied on its TXD input. For IO-Link

communication using the CQ1 transceiver in either COM2

(SR < 0.4V) or COM3 (SR > 0.9V), ensure the Q2 driver is

not in a heavy load or short-circuit condition after a wake-up

request is acknowledged and during the IO-Link start-up

phase. Master and device can thus exchange initial data

without disruption and establish communication success-

fully. Thereafter, a message sent by the master must be

answered by the device after a short delay. However, the

device might need additional time to perform operations

before it can receive upcoming messages from the master.

To support that, IO-Link defines the cycle time, the time

between master messages, configured at the master side

to meet the device timing requirements. If the device fails

to answer a message sent by the master, as a consequence

of the Q2 driver still pulsing the heavy load (disrupting

CQ1 communication), the master repeats the message up

to two additional times (waiting the cycle time between

repetitions) before re-initiating communication by sending

a new wake-up request. This master’s retry property can

be used to set an optimum cycle time for driving heavy

loads on Q2 (by request of the IO-Link master) without

breaking communication. For instance, a cycle time set to

100ms gives the Q2 driver 300ms to switch the heavy load

on fully before the device has its last chance to answer

(after 2 message failures) the repeated message from the

master successfully.

VTXEN1

5V/DIV

0V

VSC1

5V/DIV

0V

VSC2

5V/DIV

0V

VCQ1

0.2V/DIV

0V

500ms/DIV

36692 F13

Figure 13. SC1 and SC2 Waveforms in Thermal Shutdown

(CQ1 in Short-Circuit, TXEN2 Low)

For more information www.linear.com/LT3669

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