LT3669EUFD View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LT3669EUFD

IO-Link Transceiver with Integrated Step-Down Regulator and LDO

Linear Technology 

LT3669/LT3669-2

APPLICATIONS INFORMATION

LOW DROPOUT VOLTAGE REGULATOR (LDO)

FBLDO Resistor Network

The LDO output voltage is programmed with a resistor

divider between its output and the FBLDO pin. Choose the

resistor values according to:

R3 = R4





VLDO

0.794V

−

1

Reference designators refer to the Block Diagram. Use 1%

resistors to maintain output voltage accuracy.

LDO Current-Limit Foldback

The LT3669 LDO has a current-limit foldback circuit that

limits the maximum power dissipated by the LDO pass

transistor to increase its robustness. Figure 18 shows the

transfer function between current limit and voltage across

the pass transistor.

180

Stability and Output Capacitance

The LT3669 LDO requires an output capacitor for stability.

It is designed to be stable with most low ESR capacitors

(typically ceramic, tantalum or low ESR electrolytic). Use

a minimum output capacitor of 1μF with an ESR of 0.5Ω

or less to prevent oscillations. Larger values of output ca-

pacitance decrease peak deviations and provide improved

transient response for larger load current changes. Bypass

capacitors, used to decouple individual components pow-

ered by the LT3669, increase the effective output capacitor

value. If using ceramic capacitors, use X5R or X7R types.

LDO Input Considerations

For optimum efficiency and highest output current capabil-

ity, connect the LDO input to the lowest possible available

supply that guarantees a regulated output voltage, taking

into account the maximum LDO dropout voltage of 750mV.

If the programmed output of the switching regulator satis-

fies this condition, that supply could be a good choice.

Otherwise, if no other low supply is available, then it can

be connected to the DIO pin. If a bypass capacitor between

LDOIN and GND is needed in this configuration, connect an

external diode between L+ and DIO to prevent damage on

the internal reverse-polarity diode due to surge currents

during hot plugging. To guarantee full reverse-polarity

protection, do not connect LDOIN directly to L+.

35

0

0

6

35

VLDOIN – VLDO (V)

36692 F18

Figure 18. LDO Current Limit Foldback

Minimum LDO Load Current

The LT3669 LDO requires a minimum of 175µA load current

to prevent its output from rising above the programmed

voltage. It is recommended to choose the feedback resis-

tors to meet this requirement (for example, R4 and R3 of

4.42kΩ and 14kΩ, respectively, for a 3.3V output voltage).

LDO Minimum L+ Voltage

The LDO’s error amplifier is supplied from the L+ pin. A

minimum L+ to LDO voltage difference of 4V is required

to guarantee a regulated LDO output. For instance, for an

LDO programmed output voltage of 3.3V, a minimum of

7.3V at the L+ pin would meet the requirement.

3669fa

26

For more information www.linear.com/LT3669

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