AD5370BSTZ-REEL View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5370BSTZ-REEL

40-Channel,16-Bit, Serial Input, Voltage Output DAC

Analog Devices 

Pin No.

16, 35

17, 36

51, 58

52, 57

53

54

55

56

59

63

64

AD5370

Mnemonic

VDD

VSS

DGND

DVCC

SYNC

SCLK

SDI

SDO

AGND

LDAC

CLR

Exposed Paddle

Description

Positive Analog Power Supply; +9 V to +16.5 V for specified performance. These pins

should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.

Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins

should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.

Ground for All Digital Circuitry. Both DGND pins should be connected to the DGND plane.

Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic

capacitors and 10 μF capacitors.

Active Low Input. This is the frame synchronization signal for the serial interface. See the

Timing Characteristics section for more details.

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This

pin operates at clock speeds up to 50 MHz. See the Timing Characteristics section for

more details.

Serial Data Input. Data must be valid on the falling edge of SCLK. See the Timing

Characteristics section for more details.

Serial Data Output for SPI Interface. CMOS output. SDO can be used for readback. Data is

clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.

Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane.

Load DAC Logic Input (Active Low).

Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for

more information.

The lead-free chip scale package (LFCSP) has an exposed paddle on the underside. The

paddle should be connected to VSS.

Rev. 0 | Page 11 of 28

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