AD5370BSTZ-REEL View Datasheet(PDF) - Analog Devices
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Description
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AD5370BSTZ-REEL Datasheet PDF : 28 Pages
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AD5370
THEORY OF OPERATION
DAC ARCHITECTURE
The AD5370 contains 40 DAC channels and 40 output amplifiers
in a single package. The architecture of a single DAC channel
consists of a 16-bit resistor-string DAC followed by an output
buffer amplifier. The resistor-string section is simply a string of
resistors, of equal value, from VREF to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit binary
digital code loaded to the DAC register determines at which
node on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the DAC
output voltage by 4. The nominal output span is 12 V with a 3 V
reference and 20 V with a 5 V reference.
CHANNEL GROUPS
The 40 DAC channels of the AD5370 are arranged into five
groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 4 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.
Table 7. AD5370 Registers
Register
Name
Word
Length Default
(Bits) Value
X1A
16
0x1555
X1B
16
0x1555
M
16
0x3FFF
C
16
0x2000
X2A
16
Not user
accessible
X2B
16
Not user
accessible
DAC
Not user
accessible
OFS0
14
0x1555
OFS1
14
0x1555
Control
3
0x00
A/B Select 0 8
A/B Select 1 8
A/B Select 2 8
A/B Select 3 8
A/B Select 4 8
0x00
0x00
0x00
0x00
0x00
Description
Input Data Register A. One for each DAC channel.
Input Data Register B. One for each DAC channel.
Gain trim register. One for each DAC channel.
Offset trim register. One for each DAC channel.
Output Data Register A. One for each DAC channel. These registers store the final calibrated DAC
data after gain and offset trimming. They are not readable or directly writable.
Output Data Register B. One for each DAC channel. These registers store the final calibrated DAC
data after gain and offset trimming. They are not readable or directly writable.
Data registers from which the DAC channels take their final input data. The DAC registers are
updated from the X2A or X2B register. They are not readable or directly writable.
Offset DAC 0 data register. Sets the offset for Group 0.
Offset DAC 1 data register. Sets the offset for Group 1 to Group 4.
Bit 2 = A/B.
0 = global selection of X1A input data registers.
1 = X1B registers.
Bit 1 = enable temperature shutdown.
0 = disable temperature shutdown.
1 = enable.
Bit 0 = soft power-down.
0 = soft power-up.
1 = soft power-down.
Each bit in this register determines if a DAC channel in Group 0 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC channel in Group 1 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC channel in Group 2 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC channel in Group 3 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC channel in Group 4 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Rev. 0 | Page 15 of 28
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