OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
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Description
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OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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ORCA Series 2 FPGAs
Data Sheet
November 2006
FPGA States of Operation
operating voltage (4.75 V for OR2CxxA commercial
devices and 3.0 V for OR2TxxA/B devices).
Prior to becoming operational, the FPGA goes through a At the end of initialization, the default configuration
sequence of states, including initialization, configuration, option is that the configuration RAM is written to a low
and start-up. Figure 36 outlines these three FPGA
state. This prevents shorts prior to configuration. As a
states.
POWERUP
– POWER-ON TIME DELAY
S INITIALIZATION
– CLEAR CONFIGURATION MEMORY
– INIT LOW, HDC HIGH, LDC LOW
ICE YES
BIT
ERROR
D NO
RESET,
INIT,
OR
PRGM
LOW
NO
YES
V CONFIGURATION
E – M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME WRITTEN
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
RESET
OR
PRGM
LOW
DE U START-UP
IN – ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
PRGM
LOW
T T OPERATION
C 5-4529(F).r6
N Figure 36. FPGA States of Operation
E O Initialization
L Upon powerup, the device goes through an initialization
E C process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When VDD reaches the
voltage at which portions of the FPGA begin to operate
S IS (2.5 V to 3 V for the OR2CxxA, 2.2 V to 2.7 V for the
OR2TxxA/OR2TxxB), the I/Os are configured based on
the configuration mode, as determined by the mode
D select inputs M[2:0]. A time-out delay is initiated when
configuration option, after the first configuration (i.e., at
reconfiguration), the user can reconfigure without
clearing the internal configuration RAM first.
The active-low, open-drain initialization signal INIT is
released and must be pulled high by an external resis-
tor when initialization is complete. To synchronize the
configuration of multiple FPGAs, one or more INIT pins
should be wire-ANDed. If INIT is held low by one or
more FPGAs or an external device, the FPGA remains
in the initialization state. INIT can be used to signal that
the FPGAs are not yet initialized. After INIT goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled and the FPGA enters the configuration
state.
The high during configuration (HDC), low during config-
uration (LDC), and DONE signals are active outputs in
the FPGA’s initialization and configuration states. HDC,
LDC, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
If configuration has begun, an assertion of RESET or
PRGM initiates an abort, returning the FPGA to the ini-
tialization state. The PRGM and RESET pins must be
pulled back high before the FPGA will enter the config-
uration state. During the start-up and operating states,
only the assertion of PRGM causes a reconfiguration.
In the master configuration modes, the FPGA is the
source of configuration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after INIT goes high.
When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count configuration clock
VDD reaches between 3.0 V and 4.0 V (OR2CxxA) or
cycles applied to the FPGA. As each configuration data
2.7 V to 3.0 V (OR2TxxA/2TxxB) to allow the power
frame is supplied to the FPGA, it is internally assem-
supply voltage to stabilize. The INIT and DONE outputs bled into data words. Each data word is loaded into the
are low. At powerup, if VDD does not rise from 2.0 V to internal configuration memory. The configuration load-
VDD in less than 25 ms, the user should delay configu- ing process is complete when the internal length count
ration by inputting a low into INIT, PRGM, or RESET
equals the loaded length count in the length count field,
until VDD is greater than the recommended minimum
and the required end of configuration frame is written.
42
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