OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
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OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA States of Operation (continued)
Partial Reconfiguration
All ORCA device families have been designed to allow
ATT3000
CCLK PERIOD
a partial reconfiguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
F
configuration sequence that tells the FPGA to not reset
DONE
I/O
GLOBAL
S RESET
E DONE
I/O
IC D GSRN
ACTIVE
ORCA CCLK_NOSYNC
F
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
V E ORCA CCLK_SYNC
DONE IN
E U DONE
C1, C2, C3, OR C4
I/O
Di Di + 1
Di + 2
Di + 3
D IN GSRN
ACTIVE
Di Di + 1
Di + 2
Di + 3
F
Di + 4
Di + 4
T T UCLK
C DONE
N I/O
E GSRN
O ACTIVE
ORCA UCLK_NOSYNC
F
C1 U1
U2
U3
U4
U1
U2
U3
U4
U1
U2
U3
U4
LORCA UCLK_SYNC
SE ISC DONE
I/O
D GSRN
DONE IN
C1 U1, U2, U3, OR U4
F
Di Di + 1 Di + 2 Di + 3 Di + 4
all of the configuration RAM during a reconfiguration.
Then only the configuration frames that are to be modi-
fied need to be rewritten, thereby reducing the configu-
ration time.
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconfiguration is being done. If this is done, the
user must be careful to not cause contention between
the two configurations (the bit stream resident in the
FPGA and the partial reconfiguration bit stream) as the
second reconfiguration bit stream is being loaded.
Other Configuration Options
Configuration options used during device start-up were
previously discussed in the FPGA States of Operation
section of this data sheet. There are many other config-
uration options available to the user that can be set
during bit stream generation in ispLEVER. These
include options to enable boundary scan, readback
options, and options to control and use the internal
oscillator after configuration.
Other useful options that affect the next configuration
(not the current configuration process) include options
to disable the global set/reset during configuration, dis-
able the 3-state of I/Os during configuration, and dis-
able the reset of internal RAMs during configuration to
allow for partial configurations (see above). For more
information on how to set these and other configuration
options, please see the ispLEVER documentation.
Configuration Data Format
The ispLEVER development system interfaces with
front-end design entry tools and provides the tools to
produce a fully configured FPGA. This section dis-
cusses using the ispLEVER development system to
generate configuration RAM data and then provides
ACTIVE
Di Di + 1 Di + 2 Di + 3
the details of the configuration frame format.
UCLK PERIOD
SYNCHRONIZATION UNCERTAINTY
F = finished, no more CLKs required.
The ORCA Series 2 series of FPGAs are enhanced
versions of the ORCA ATT2Cxx/ATT2Txx architectures
that provide upward bit stream compatibility for both
5-2761(F).r4 series of devices as well as with each other.
Figure 38. Start-Up Waveforms
Lattice Semiconductor
45
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