ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

Doc. Rev.

11121C Comments

Change

Request

Ref.

Section 49. “Pulse Width Modulation Controller (PWM)”

Editorial and formatting changes throughout; replaced instances of “Read-write” with “Read/Write”

Section 49.6.2.2 “Comparator”: corrected PWM waveform period formulas

rfo

9123

Table 6-1 “Fault Inputs”: in “Polarity Level” column, replaced all instances of “1” with “To be configured to 1” rfo

Section 49.6.5.4 “Changing the Synchronous Channels Update Period”: removed cross-reference to section rfo

“Method 3: Automatic write of duty-cycle values and automatic trigger of the update” from first paragraph

Section 49.6.1 “PWM Clock Generator”: replaced instances of “F” with “f” when used to represent frequency rfo

Section 49.6.5.7 “Register Write Protection”: at end of section, replaced sentence “The WPVS and

rfo

PWM_WPSR fields are automatically reset after reading the PWM_WPSR register” with “The WPVS and

WPVSRC fields are automatically cleared after reading the PWM_WPSR”

Section 49.7.9 “PWM Sync Channels Mode Register”: removed table row for value 3 “reserved” in UPDM field rfo

description

Section 49.7.30 “PWM Write Protection Control Register”: updated WPKEY and WPCMD field descriptions 8849

Section 50. “Analog-to-Digital Converter (ADC)”

Editorial and formatting changes throughout

Added title to Figure 50-6 “Hardware Trigger Delay”

8997

Section 50.5.8 “Conversion Performances”: updated wording (‘see the product DC Characteristics section’ --> 9184

‘see the product electrical characteristics’)

Section 50.8.25 “ADC Write Protect Mode Register”: updated WPKEY field description

8856

Section 51. “True Random Number Generator (TRNG)”

Figure 51-1 “TRNG Block Diagram”: reformatted graphics to improve readability

Section 51.4.1 “Power Management”: minor editorial changes

Section 51.5 “Functional Description”: minor editorial changes

Section 51.6.1 “TRNG Control Register”: updated KEY field description

9001

rfo

rfo

8843

Section 52. “Advanced Encryption Standard (AES)”

Editorial and minor formatting changes throughout

Section 52.2 “Embedded Characteristics”: added bullet “Double Input Buffer Optimizes Runtime”

9076

Added Section 52.4.2 “Double Input Buffer”

Table 52-4 “Last Output Data Mode Behavior versus Start Modes”

- reorganized order of rows

9076

9103

- replaced “Not available” with “At the address specified in the Channel Buffer Transfer Descriptor” in row

Encrypted/Decrypted Data Result Location at DMA Transfer LOD = 0

Section 52.6.2 “AES Mode Register”:

- updated CKEY field description

- updated LOD field description

- added field DUALBUFF

Section 52.6.10 “AES Initialization Vector Register x”: updated IV field description

8859

9103

9076

8892

Section 53. “Triple Data Encryption Standard (Triple DES)”: No changes

Section 54. “Secure Hash Algorithm (SHA)”: No changes

SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

1903

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