ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

11.2 Flow Diagram

The ROM code implements the algorithm shown in Figure 11-1.

Figure 11-1. ROM Code Algorithm Flow Diagram

Chip Setup

Valid boot code

Yes

found in one

NVM

No

SAM-BA Monitor

Copy and run it

in internal SRAM

11.3

Chip Setup

At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz fast RC oscillator.

Initialization follows the steps described below:

1. Stack Setup for ARM supervisor mode

2. Main Oscillator Detection: The Main Clock is switched to the 32 kHz RC oscillator to allow external clock

frequency to be measured. Then the Main Oscillator is enabled and set in the bypass mode. If the

MOSCSELS bit rises, an external clock is connected, and the next step is Main Clock Selection (3). If not,

the bypass mode is cleared to attempt external quartz detection. This detection is successful when the

MOSCXTS and MOSCSELS bits rise, else the internal 12 MHz fast RC oscillator is used as the Main Clock.

3. Main Clock Selection: The Master Clock source is switched from the Slow Clock to the Main Oscillator

without prescaler. The PMC Status Register is polled to wait for MCK Ready. PCK and MCK are now the

Main Clock.

4. C Variable Initialization: Non zero-initialized data is initialized in the RAM (copy from ROM to RAM). Zero-

initialized data is set to 0 in the RAM.

5. PLLA Initialization: PLLA is configured to get a PCK at 96 MHz and an MCK at 48 MHz. If an external clock

or crystal frequency running at 12, 16, 24 or 48 MHz is found, then the PLLA is configured to allow

communication on the USB link for the SAM-BA Monitor; else the Main Clock is switched to the internal

12 MHz fast RC oscillator, but USB will not be activated.

64 SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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