ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

Externally generated errors during data read are always synchronous. The address captured in the DFAR matches

the address which generated the external abort.

9.5.6.2 Synchronous and Asynchronous Aborts

Chapter 4, System Control in the Cortex-A5 Technical Reference Manual describes synchronous and

asynchronous aborts, their priorities, and the IFSR and DFSR. To determine a fault type, read the DFSR for a data

abort or the IFSR for an instruction abort.

The processor supports an Auxiliary Fault Status Register for software compatibility reasons only. The processor

does not modify this register because of any generated abort.

9.5.7

MMU Software Accessible Registers

The system control coprocessor registers, CP15, in conjunction with page table descriptors stored in memory,

control the MMU.

Access all the registers with instructions of the form:

MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>

MCR p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>

CRn is the system control coprocessor register. Unless specified otherwise, CRm and Opcode_2 Should Be Zero.

SAMA5D3 Series [DATASHEET]

51

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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