ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

10.6 Functional Description

10.6.1 Test Pin

One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied

at low level to ensure normal operating conditions. Other values associated with this pin are reserved for

manufacturing test.

10.6.2 EmbeddedICE

The Cortex-A5 EmbeddedICE-RT is supported via the ICE/JTAG port. It is connected to a host computer via an

ICE interface.The internal state of the Cortex-A5 is examined through an ICE/JTAG port which allows instructions

to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug

state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the Cortex-

A5 registers. This data can be serially shifted out without affecting the rest of the system.

There are two scan chains inside the Cortex-A5 processor which support testing, debugging, and programming of

the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port.

EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG

operations. A chip reset must be performed after JTAGSEL is changed.

For further details on the EmbeddedICE-RT, see the ARM document:

ARM IHI 0031A_ARM_debug_interface_v5.pdf

10.6.3 JTAG Signal Description

TMS is the Test Mode Select input which controls the transitions of the test interface state machine.

TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction

Register, or other data registers).

TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment

controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and

propagates them to the next chip in the serial test circuit.

NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to

reset the debug logic. On Atmel Cortex-A5-based cores, NTRST is a Power On Reset output. It is asserted on

power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK

periods.

TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test

and not by the tested device. It can be pulsed at any frequency.

10.6.4 Chip Access Using JTAG Connection

The JTAG connection is not enabled by default on this chip at delivery due to the secure ROM code

implementation.

By default, the SAMA5D3 devices boot in Standard mode and not in Secure mode. When the secure ROM code

starts, it disables the JTAG access for the entire boot sequence.

If the secure ROM code does not find any program in the external memory, it enables the USB connection and the

serial port and waits for a dedicated command to switch the chip into Secure mode.

If any other character is received, the secure ROM code starts the standard SAM-BA monitor, locks access to the

ROM memory, and enables the JTAG.

The chip can then be accessed using the JTAG connection.

SAMA5D3 Series [DATASHEET]

57

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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