10.4.2 Test Environment
Figure 10-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this
example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be
connected to form a single scan chain.
Figure 10-3. Application Test Environment Example
Test Adaptor
Tester
JTAG
Interface
ICE/JTAG Chip n
Chip 2
SAM device
Chip 1
SAM-based Application Board In Test
SAMA5D3 Series [DATASHEET]
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Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16