VPOS
TP2
R6
C2
0⍀ 0.01F
VS
A
B
RFIN
SW2
C1
100pF
R2
75⍀
VPOS
A
B SW1
C3
100pF
AD8361
1 VPOS SREF 8
VS
SW3 A
B
2 IREF VRMS 7
C5
3 RFIN FLTR 6
VPOS
1nF
4 PWDN COMM 5
TP1
R5
(OPEN)
R4
0⍀
C4
(OPEN)
Vrms
Figure 43. Evaluation Board Schematic micro_SOIC
AD8361
J2
R4
0⍀
C4
OPEN
R5
OPEN
AD8361
1 VRMS VPOS 6
2 COMM RFIN 5
3 FLTR PWDN 4
C5
1nF
TP1
J3
C3
C2
100pF 0.01F
TP2 VPOS
J1
C1
100pF
R2
75⍀
1
SW1
3
2
R7
50⍀
Figure 46. Evaluation Board Schematic, SOT-23-6L
Figure 44. Layout of Component Side micro_SOIC
Figure 47. Layout of the Component Side, SOT-23-6L
Figure 45. Silkscreen of Component Side micro_SOIC
Figure 48. Silkscreen of the Component Side, SOT-23-6L
REV. A
–15–