AD5338RBCPZ-RL7(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5338RBCPZ-RL7
(Rev.:Rev0)

Dual, 10-Bit nanoDAC with 2 ppm/°C Reference, I2C Interface

Analog Devices 

AD5338R

SERIAL INTERFACE

The AD5338R has a 2-wire I2C-compatible serial interface (refer

to I2C-Bus Specification, Version 2.1, January 2000, available from

Philips Semiconductor). See Figure 2 for a timing diagram of a

typical write sequence. The AD5338R can be connected to an I2C

bus as a slave device, under the control of a master device. The

AD5338R can support standard (100 kHz) and fast (400 kHz) data

transfer modes. Support is not provided for 10-bit addressing and

general call addressing.

Input Shift Register

The input shift register of the AD5338R is 24 bits wide. Data is

loaded into the device as a 24-bit word under the control of

a serial clock input, SCL. The first eight MSBs make up the

command byte. The first four bits are the command bits (C3, C2,

C1, and C0) that control the mode of operation of the device

(see Table 7). The last four bits of the first byte are the address bits

(DAC B, 0, 0, and DAC A, see Table 8).

The data-word comprises 10-bit input code, followed by six don’t

care bits for the AD5338R. These data bits are transferred to the

input register on the 24 falling edges of SCL.

Commands can be executed on the individual DAC channels or

on both DACs, depending on the address bits selected.

Table 7. Command Definitions

Command

C3 C2 C1 C0 Description

0 0 0 0 No operation

0 0 0 1 Write to Input Register n (dependent

on LDAC)

0 0 1 0 Update DAC Register n with contents of

Input Register n

0 0 1 1 Write to and update DAC Channel n

0 1 0 0 Power down/power up DAC

0 1 0 1 Hardware LDAC mask register

0 1 1 0 Software reset (power-on reset)

0 1 1 1 Internal reference setup register

1 0 0 0 Reserved

… … … … Reserved

1 1 1 1 Reserved

Data Sheet

Table 8. Address Commands

Selected DAC Channel

DAC B DB18 DB17 DAC A

0

0

0

1

1

0

0

0

1

0

0

1

Description

DAC A

DAC B

DAC A and DAC B

WRITE AND UPDATE COMMANDS

Write to Input Register n (Dependent on LDAC)

Command 0001 allows the user to write to the dedicated input

register of each DAC individually. When LDAC is low, the input

register is transparent (if not controlled by the LDAC mask

register).

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the contents

of the input registers selected and updates the DAC outputs

directly.

Write to and Update DAC Channel n (Independent of LDAC)

Command 0011 allows the user to write to the DAC registers and

update the DAC outputs directly.

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3 C2 C1 C0 DAC B 0

0 DAC A D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X

X

X

X

X

X

COMMAND

DAC ADDRESS

DAC DATA

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

Figure 43. Input Shift Register Content

DATA LOW BYTE

Rev. 0 | Page 18 of 28

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