AD5338RBCPZ-RL7(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5338RBCPZ-RL7
(Rev.:Rev0)

Dual, 10-Bit nanoDAC with 2 ppm/°C Reference, I2C Interface

Analog Devices 

Data Sheet

AD5338R

SERIAL OPERATION

The AD5338R has a 7-bit slave address. The five MSBs are 00011

and the two LSBs (A1 and A0) are set by the state of the A0 and

A1 address pins. The ability to make hardwired changes to A0

and A1 allows the user to incorporate up to four of these devices

on one bus, as outlined in Table 9.

Table 9. Device Address Selection

A0 Pin Connection

A1 Pin Connection

GND

GND

VLOGIC

GND

GND

VLOGIC

VLOGIC

VLOGIC

A0 A1

0

0

1

0

0

1

1

1

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address. The slave

address corresponding to the transmitted address responds

by pulling SDA low during the 9th clock pulse (this is termed

the acknowledge bit). At this stage, all other devices on the

bus remain idle while the selected device waits for data to

be written to, or read from, its shift register.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

The transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of SCL.

3. When all data bits have been read or written, a stop condition

is established. In write mode, the master pulls the SDA line

high during the 10th clock pulse to establish a stop condition.

In read mode, the master issues a no acknowledge for the

9th clock pulse (that is, the SDA line remains high). The

master then brings the SDA line low before the 10th clock

pulse, and then high during the 10th clock pulse to establish

a stop condition.

WRITE OPERATION

When writing to the AD5338R, the user must begin with a start

command followed by an address byte (R/W = 0), after which

the DAC acknowledges that it is prepared to receive data by

pulling SDA low. The AD5338R requires two bytes of data for the

DAC and a command byte that controls various DAC functions.

Three bytes of data must, therefore, be written to the DAC with the

command byte followed by the most significant data byte and

the least significant data byte, as shown in Figure 44. All these data

bytes are acknowledged by the AD5338R. A stop condition follows.

1

9

1

9

SCL

SDA

0

0

START BY

MASTER

1

SCL

(CONTINUED)

0

1

1 A1

FRAME 1

SLAVE ADDRESS

A0 R/W

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16

ACK. BY

AD5338R

9

1

FRAME 2

COMMAND BYTE

ACK. BY

AD5338R

9

SDA

(CONTINUED)

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB7 DB6

FRAME 3

MOST SIGNIFICANT

DATA BYTE

ACK. BY

AD5338R

Figure 44. I2C Write Operation

DB5 DB4 DB3 DB2 DB1

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

DB0

ACK. BY STOP BY

AD5338R MASTER

Rev. 0 | Page 19 of 28

Share Link: