AD5338ARMZ-1(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5338ARMZ-1
(Rev.:RevA)

2.5 V to 5.5 V, 250 µA, 2-Wire Interface Dual-Voltage Output, 8-/10-/12-Bit DACs

Analog Devices 

AD5337/AD5338/AD5339

Grade A

Grade B

Parameter1

Min Typ

Max

Min Typ

Max

Unit

LOGIC INPUTS (A0)5

Input Current

±1

±1

µA

VIL, Input Low Voltage

0.8

0.8

V

0.6

0.6

V

0.5

0.5

V

VIH, Input High Voltage

2.4

2.4

V

2.1

2.1

V

2.0

2.0

V

Pin Capacitance

3

3

pF

LOGIC INPUTS (SCL, SDA)5

VIH, Input High Voltage

0.7

VDD

VDD +

0.7

0.3

VDD

VDD +

V

0.3

VIL, Input Low Voltage

−0.3

+0.3

–0.3

VDD

+0.3

V

VDD

IIN, Input Leakage Current

±1

±1

µA

VHYST, Input Hysteresis

0.05

0.05

V

VDD

VDD

CIN, Input Capacitance

8

8

pF

Glitch Rejection

50

50

ns

LOGIC OUTPUT (SDA)5

VOL, Output Low Voltage

Three-State Leakage

Current

Three-State Output

8

Capacitance

POWER REQUIREMENTS

VDD

2.5

IDD (Normal Mode)7

VDD = 4.5 V to 5.5 V

300

VDD = 2.5 V to 3.6 V

250

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V

0.2

0.4

0.6

±1

8

5.5

2.5

375

300

350

250

1.0

0.2

0.4

V

0.6

V

±1

µA

pF

5.5

V

375

µA

350

µA

1.0

µA

VDD = 2.5 V to 3.6 V

0.08

1.00

0.08

1.00

µA

B Version2 Conditions/Comments

VDD = 5 V ±10%

VDD = 3 V ±10%

VDD = 2.5 V

VDD = 5 V ±10%

VDD = 3 V ±10%

VDD = 2.5 V

SMBus-compatible at VDD < 3.6 V

SMBus-compatible at VDD < 3.6 V

Input filtering suppresses noise spikes of

less than 50 ns

ISINK = 3 mA

ISINK = 6 mA

VIH = VDD and VIL = GND

VIH = VDD and VIL = GND

IDD = 4 µA (max) during 0 readback

on SDA

IDD = 1.5 µA (max) during 0 readback

on SDA

1 For explanations of the specific parameters, see the Terminology section.

2 Temperature range: (A and B versions): −40°C to +105°C; typical at 25°C.

3 DC specifications tested with the outputs unloaded.

4 Linearity is tested using a reduced code range: AD5337 (Codes 8 to 248); AD5338, AD5338-1 (Codes 28 to 995); AD5339 (Codes 115 to 3981).

5 Guaranteed by design and characterization; not production tested.

6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be

positive.

7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.

Rev. A | Page 4 of 24

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