EVAL-AD7767-1EDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
EVAL-AD7767-1EDZ Datasheet PDF : 24 Pages
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AD7767
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF = 5 V, common-mode input = VREF/2, TA = −40°C (TMIN) to +105°C (TMAX),
unless otherwise noted 1
Table 3.
Parameter
DRDY Operation
t1
t2 2
t3
t4
t5
tREAD 3
tDRDY 3
Read Operation
t6
t7
t8
t9
t10
t11
tSCLK
t12
t13
Read Operation with CS Low
t14
t15
Daisy Chain Operation
t16
t17
SYNC/PD Operation
t18
t19
t20
t21
tSETTLING3
Limit at TMIN, TMAX
510
100
900
265
128
71
294
435
492
tDRDY − t5
n × 8 × tMCLK
0
6
60
50
25
24
10
10
10
1/t8
6
0
0
0
1
2
1
20
1
510
592 × (n + 2)
Unit Description
ns typ
ns min
ns max
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
MCLK rising edge to DRDY falling edge
MCLK high pulse width
MCLK low pulse width
MCLK rising edge to DRDY rising edge (AD7767)
MCLK rising edge to DRDY rising edge (AD7767-1)
MCLK rising edge to DRDY rising edge (AD7767-2)
DRDY pulse width (AD7767)
DRDY pulse width (AD7767-1)
DRDY pulse width (AD7767-2)
DRDY low period, read data during this period
ns typ DRDY period
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
ns min
min
ns max
ns min
DRDY falling edge to CS setup time
CS falling edge to SDO three-state disabled
Data access time after SCLK falling edge (VDRIVE = 1.7 V)
Data access time after SCLK falling edge (VDRIVE = 2.3 V)
Data access time after SCLK falling edge (VDRIVE = 2.7 V)
Data access time after SCLK falling edge (VDRIVE = 3.0 V)
SCLK falling edge to data valid hold time (VDRIVE = 3.6 V)
SCLK high pulse width
SCLK low pulse width
Minimum SCLK period
Bus relinquish time after CS rising edge
CS rising edge to DRDY rising edge
ns min DRDY falling edge to data valid setup time
ns max DRDY rising edge to data valid hold time
ns min SDI valid to SCLK falling edge setup time
ns max SCLK falling edge to SDI valid hold time
ns typ
ns typ
ns min
ns typ
tMCLK
SYNC/PD falling edge to MCLK rising edge
MCLK rising edge to DRDY rising edge going into SYNC/PD
SYNC/PD rising edge to MCLK rising edge
MCLK rising edge to DRDY falling edge coming out of SYNC/PD
Filter settling time after a reset or power-down
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V.
2 t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum
MCLK frequency is 1.024 MHz.
3 n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2.
Rev. 0 | Page 5 of 24
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