EVAL-AD7767-1EDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
EVAL-AD7767-1EDZ Datasheet PDF : 24 Pages
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AD7767
TIMING DIAGRAMS
MCLK
t2
1
8×n
1
t3
t4
8×n
t1
t5
t5
DRDY
tREAD
tDRDY
Figure 2. DRDY vs. MCLK Timing Diagram, n = 1 for AD7767 (Decimate by 8), n = 2 for AD7767-1 (Decimate by 16), n = 4 for AD7767-2 (Decimate by 32)
DRDY
CS
SCLK
SDO
tDRDY
tREAD
t6
t13
1
t7
t8
t10
t9
t11
23
t12
MSB
D22
D21
D20
D1
LSB
Figure 3. Serial Timing Diagram, Reading Data Using CS
CS = 0
DRDY
SCLK
SDO
t14
1
t8
DATA
INVALID
MSB
D22
tDRDY
tREAD
t10
t11
t9
D21
D20
23
D1
24
t15
LSB
DATA
INVALID
Figure 4. Serial Timing Diagram, Reading Data Setting CS Logic Low
Rev. 0 | Page 6 of 24
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