AD8364ACPZ-WP(RevB) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD8364ACPZ-WP Datasheet PDF : 44 Pages
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AD8364
Data Sheet
VPOS
C11
0.1µF
C5
0.1µF
INPA
1:4
C10
100pF
C7
T2
0.1µF
C6
0.1µF
VPOS
R24
0Ω
C23
100pF
C13
R5
0.1µF
0Ω
C8
0.1µF
C12
100pF
C9
0.1µF
C14
0.1µF
24
23
22
21
20
19
18
17
CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA
25 VPSA
VSTA 16
26 INHA
27 INLA
28 PΩDN
AD8364ACPZ
OUTA 15
FBKA 14
OUTP 13
OUTA
OUTP
T1
1:4
INPB
C2
0.1µF
C4
0.1µF
29 COMR
30 INLB
OUTN 12
FBKB 11
C3
0.1µF
31 INHB
32 VPSB
EXPOSED PADDLE
OUTB 10
VSTB 9
VPOS
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
C20
1
2
3
4
5
6
7
8
100pF C22
C19
C16
0.1µF
R201 R181 0.1µF
0.1µF
C21
0.1µF C1
0.1µF
C24
100pF
R191
R171
1SEE TEXT.
OUTN
OUTB
Figure 60. Basic Connections for Operation in Measurement Mode
CONTROLLER MODE BASIC CONNECTIONS
In addition to being a measurement device, the AD8364 can
also be configured to measure and control rms signal levels. The
AD8364 has two controller modes. Each of the two rms log
detectors can be separately configured to set and control the
output power level of a variable gain amplifier (VGA) or
variable voltage attenuator (VVA). Alternatively, the two rms
log detectors can be configured to measure and control the gain
of an amplifier or signal chain.
Automatic Power Control
Figure 61 shows how the device should be reconfigured to
control output power.
The RF input to the device is configured as before. A directional
coupler taps off some of the power being generated by the VGA
(typically a 10 dB to 20 dB coupler is used). A power splitter can
be used instead of a directional coupler if there are no concerns
about reflected energy from the next stage in the signal chain.
Some additional attenuation may be required to set the
maximum input signal at the AD8364 to be equal to the
recommended maximum input level for optimum linearity and
temperature stability at the frequency of operation.
VSTA and OUTA are no longer shorted together. OUTA now
provides a bias or gain control voltage to the VGA. The gain
control sense of the VGA must be negative and monotonic, that
is, increasing voltage tends to decrease gain. However, the gain
control transfer function of the device does not need to be well
controlled or particularly linear. If the gain control sense of the
VGA is positive, an inverting op amp circuit with a dc offset
shift can be used between the AD8364 and the VGA to keep the
gain control voltage in the 0 V to 5 V range.
VSTA becomes the setpoint input to the system. This can be
driven by a DAC, as shown in Figure 61, if the output power is
expected to vary, or it can simply be driven by a stable reference
voltage if constant output power is required. This DAC should
have an output swing that covers the 0 V to 3.5 V range.
Rev. B | Page 24 of 44
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