AD8364ACPZ-WP(RevB) View Datasheet(PDF) - Analog Devices
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AD8364ACPZ-WP Datasheet PDF : 44 Pages
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Data Sheet
When VSTA is set to a particular value, the AD8364 compares
this value to the equivalent input power present at the RF input.
If these two values do not match, OUTA increases or decreases
in an effort to balance the system. The dominant pole of the
error amplifier/integrator circuit that drives OUTA is set by the
capacitance on Pin CLPA; some experimentation may be
necessary to choose the right value for this capacitor. In general,
CLPA should be chosen to provide stable loop operation for the
complete output power control range. If the slope (in dB/V) of
the gain control transfer function of the VGA is not constant,
CLPA must be chosen to guarantee a stable loop when the gain
control slope is at its maximum. On the other hand, CLPA must
provide adequate averaging to the internal low range squaring
detector so that the rms computation is valid. Larger values of
CLPA tend to make the loop less responsive.
The relationship between VSTA and the RF input follows from
the measurement mode behavior of the device. For example,
from Figure 9, which shows the measurement mode transfer
function at 880 MHz, it can be seen that an input power of
−10 dBm yields an output voltage of 2.5 V. Therefore, in
controller mode, VSTA should be set to 2.5 V, which results in
an input power of −10 dBm to the AD8364.
VGA OR VVA
PIN
(OUTPUT POWER
DECREASES AS
VAPC INCREASES)
VAPC
(0V TO 4.9V AVAILABLE SWING)
POUT
ATTENUATOR
OUTA
INHA
AD8364
INLA
VSTA INHA
C7
0.1µF
C6
0.1µF
C5
T2
0.1µF
1:4
DAC
0V TO 3.5V
SEE TEXT
Figure 61. Operation in Controller Mode for Automatic Power Control
AD8364
Automatic Gain Control
Figure 62 shows how the AD8364 can be connected to provide
automatic gain control to an amplifier or signal chain.
Additional pins are omitted for clarity. In this configuration,
both rms detectors are connected in measurement mode with
appropriate filtering being used on CLP[A, B] to effect a valid
rms computation on both channels. OUTA, however, is also
connected to the VLVL pin of the on-board difference amplifier.
Also, the OUTP output of the difference amplifier drives a
variable gain element (either VVA or VGA) and is connected
back to the FBKA input via a capacitor so that it is operating as
an integrator.
Assume that OUTA is much bigger than OUTB. Because OUTA
also drives VLVL, this voltage is also present on the noninverting
input of the op amp driving OUTP. This results in a net current
flow from OUTP through the integrating capacitor into the
FBKA input. This results in the voltage on OUTP increasing. If
the gain control transfer function of the VVA/VGA is positive,
this increases the gain, which in turn increases the input signal
to INHB. The output voltage on the integrator continues to
increase until the power on the two input channels is equal,
resulting in a signal chain gain of unity.
If a gain other than 0 dB is required, an attenuator can be used
in one of the RF paths, as shown in Figure 62. Alternatively,
power splitters or directional couplers of different coupling
factors can be used. Another convenient option is to apply a
voltage on VLVL other than OUTA. Refer to Equation 11 and
the Controller Mode section for more detail.
If the VGA/VVA has a negative gain control sense, the OUTN
output of the difference amplifier can be used with the
integrating capacitor tied back to FBKB.
The choice of the integrating capacitor affects the response time
of the AGC loop. Small values give a faster response time but
can result in instability, whereas larger values reduce the response
time. Note that in this mode, the capacitors on CLPA and CLPB,
which perform the rms averaging function, must still be used
and also affect the loop response time.
Rev. B | Page 25 of 44
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