ADE3700XT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3700XT Datasheet PDF : 89 Pages
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ADE3700
Line Lock PLL
Table 7: Line Lock PLL Registers (Sheet 3 of 4)
Register Name
LLK_PLL_LOCK_TOL
Addr
0x0819
LLK_PLL_LOCK_LINE_NB
LLK_PLL_PH_OFFSET
0x081A
0x081B
LLK_PLL_PH_OFFSET_EN
0x081C
LLK_PLL_PULSE_HIGH_EXT
0x081D
LLK_PLL_STAT_LINES_L
LLK_PLL_STAT_LINES_H
LLK_PLL_STAT_ERROR_INC_LO
W
LLK_PLL_FINE_ERROR_WAIT
0x081E
0x081F
0x0820
0x0821
LLK_PLL_STAT_ON_VSYNC
0x0822
LLK_PLL_MFACTOR_SHADOW_L 0x0823
LLK_PLL_MFACTOR_SHADOW_U 0x0824
Mode Bits
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7]
[6]
[5]
[4:0]
R/W
[7]
[6:3]
R/W
[2:0]
R/W
[7:0]
R/W
[7:0]
[7:0]
[7:4]
R/W
[3:0]
[7:2]
R/W
[1]
R/W
[0]
R/W
[7:0]
R/W
[7:0]
Default
Description
0x20
0x30
0x0
0x0
0x0
0x0
0x10
More than lock_line_nb lines with a phase
error less than the lock_tol will set the lock
status bit, and the pll will work with the lock
time constant.
One or more lines with a phase error more
than lock_tol will reset the lock status bit,
and the pll will work with the slow time
constant.
LSB of lock tol is approx. 200ps.
Phase adjustment.
The maximum phase offset value is equal
to phase_rate[31:21] or 0x40, whichever is
higher.
phase enable
skip pulse
skip pulse at every rising edge of hsync
Reserved
0: no pulse extend
1: extend pulse (normal)
Reserved
pulse extend amount
0x0: minimum
0x7: maximum (normal)
Number of lines to statistically analyze.
0x0
0x0
0x0
0x80
0x02
Reserved
Reserved
Wait this number of CTRL_CLK cycles
before updating the PLL.
Reserved
PLL statistic synchronize on falling edge of
vsync
PLL statistic synchronize on rising edge of
vsync
Number of clocks in a line.
Registers 0x0803 and 0x0802 are
transferred to those registers according to
update_on_venab_fe.
21/89
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