ADE3700XT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3700XT

Analog LCD Display Engine for XGA and SXGA Resolutions

STMicroelectronics 

ADE3700

Sync Measurement

2.6 Sync Measurement

The Input Sync Measurement (SMEAS) block continuously detects activity from all video sources.

The module can measure the characteristics of the sync signals on any input port. The sync

measurement module reports the results of the measurements to the system microcontroller.

This portion of the sync measurement is fully synchronous on the crystal clock (XCLK). Another

block, the Sync Retiming Block (SRT), handles the asynchronous signal transfer of the incoming

sync signals.

Input Sync Functions:

q Activity Detection

q Sync Management

q Measurement

Table 9: Sync Measurement (Sheet 1 of 8)

Register Name

SMEAS_ACT_CTRL

SMEAS_ACT_H_SMPTM_L

SMEAS_ACT_H_SMPTM_H

SMEAS_ACT_V_SMPTM_L

SMEAS_ACT_V_SMPTM_H

SMEAS_ACT_H_MINEDGE

SMEAS_ACT_V_MINEDGE

SMEAS_H_TMOT_L

SMEAS_H_TMOT_H

Addr

0x0100

0x0101

0x0102

0x0103

0x0104

0x0105

0x0106

0x0107

0x0108

Mode Bits Default

Description

[7:4] 0x0

Reserved

R/W

[3]

0x0

Enable activity detection in free-running

mode.

R/W

[2]

0x0

Freeze results in free-running mode. No

meaning in one shot mode.

0: Do not freeze the results. New result will

be available on the next and subsequent

toggle of the polling bit.

1: Freeze the current results. The polling bit

will still toggle and the block continues to

free-run; however, results will not be

updated.

R/W

[1]

0x0

activity detection start.

In one-shot mode it triggers the start of a

measurement and is reset to zero when the

measurement is complete.

R/W

[0]

0x0

activity detection mode control

0: free-running

1: one shot

R/W

[7:0] 0x0

R/W

[7:0] 0x0

Sample time value for clock or hsync

activity. In units of XCLK_period*256

R/W

[7:0] 0x0

R/W

[7:0] 0x0

Sample time value for vsync activity in units

of XCLK_period*256. jj

Note: this number MUST be larger than

hsync sample time.

R/W

[7:0] 0x0

Minimum edge count value for clk or hsync

activity.

R/W

[7:0] 0x0

Minimum edge count value for vsync

activity.

R/W

[7:0] 0x4000 timeout counter value for clk or horizontal

R/W

[7:0]

measurement in XCLKs

25/89

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