ADE3250 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3250

LCD Display Engines with Integrated DVI, ADC and YUV Ports

STMicroelectronics 

Global Control Block

Register Name

GLBL_SCLK_SYNTH_CTRL

GLBL_SCLK_MD_SD

GLBL_SCLK_PE_L

GLBL_SCLK_PE_H

GLBL_TST_CTRL

GLBL_ADC_CLK_SRC_SEL

GLBL_SCLK_CTRL

GLBL_TCON_BPAD_EN

ADE3XXX

Table 4: Global Registers (Sheet 3 of 4)

Addr.

0x0009

Mode

R/W

R/W

R/W

R/W

0x000A R/W

R/W

0x000B R/W

0x000C R/W

0x000D

R/W

R/W

0x0010

R/W

R/W

0x0011 R/W

Bits

[7:5]

[4:3]

[2]

[1]

[0]

[7:3]

[2:0]

[7:0]

[7:0]

[7:1]

[0]

[7:3]

[2:0]

[7:5]

[4]

[3]

[2:0]

[7:0]

Default

Description

0x0 Reserved

0x0 XTAL frequency multiplier NDIV

0x0: fXCLK = 54MHz

0x1: fXCLK = 27MHz (normal)

0x2: fXCLK = 13.5MHz

0x3: Reserved

0x0 SCLK frequency synthesizer EXT_PLL

(normal operation = 0)

0x0 SCLK frequency synthesizer PLL_SEL

(normal operation = 1)

0x1 SCLK freq synth control disable (normal

operation = 0)

0x0 SCLK frequency synthesizer MD, range is

[16,31]

0x0 SCLK frequency synthesizer SDIV, range is

[0,7]

0x0 SCLK frequency synthesizer PE, range is [0,

32767]

0x0 Reserved

0x0 Functional Test Mode Enable

Reserved

0x5 ADC Sample Clock Source

0x0: YUVCLK pin

0x1: LLK_PLL (normal)

0x2: SCLK freq synth

0x3: CLKIN pin

0x4: FM freq synth

0x5: Crystal Clock

0x6: 0

0x7: Reserved

0x0 Reserved

0x0 Invert SCLK

Reserved

0x0 SCLK source select

0x0: YUVCLK pin

0x1: SCLK freq synth

0x2: FM freq synth (normal)

0x3: inclk source

0x4: CLKIN pin

0x5: crystal clock

0x6: 0

0x7: Reserved

0x0 For each bit n (0 to 7),

0: TCON[n] pin is TCON output

1: TCON[n] pin is input into TVI block

16/88

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