ADE3250 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3250 Datasheet PDF : 88 Pages
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Line Lock PLL Block
ADE3XXX
Table 7: Line Lock PLL Registers (Sheet 2 of 4)
Register Name
LLK_PLL_CTRL
Addr
0x0801
LLK_PLL_MFACTOR_L
LLK_PLL_MFACTOR_H
LLK_PLL_HPERIOD_L
LLK_PLL_HPERIOD_H
LLK_PLL_PHASE_RATE_INIT_0
LLK_PLL_PHASE_RATE_INIT_1
0x0802
0x0803
0x0804
0x0805
0x0806
0x0807
LLK_PLL_PHASE_RATE_INIT_2
LLK_PLL_PHASE_RATE_INIT_3
LLK_PLL_PHASE_RATE_INIT_WR
0x0808
0x0809
0x080A
LLK_PLL_TC_AEF
LLK_PLL_TC_BEF
LLK_PLL_TC_ALF
LLK_PLL_TC_BLF
LLK_PLL_TC_AES
LLK_PLL_TC_BES
LLK_PLL_TC_ALS
0x080B
0x080C
0x080D
0x080E
0x080F
0x0810
0x0811
Mode Bits
R/W
[7:6]
R/W
[5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:1]
[0]
[7:4]
R/W
[3:0]
[7:4]
R/W
[3:0]
[7:6]
R/W
[5:0]
[7:6]
R/W
[5:0]
[7:4]
R/W
[3:0]
[7:4]
R/W
[3:0]
[7:6]
R/W
[5:0]
Default
Description
Reserved
0x0
0: normal
1: diagnostic mode -- PLL uses only fine
error
0x0
0: normal
1: diagnostic -- coarse error is multiplied by
2
0x0
input hsync edge selection
0: rising edge
1: falling edge
0x0
sync on green input selection
0: composite sync (HSYNC pin)
1: sync on green (CSYNC pin)
0x0
0: normal
1: divide PLL clock by 2
0x0
0x0280
0: normal
1: Free-running mode
number of clocks in a line
0x0040 pulse width of synthetic hsync
0x0
Initial Phase Rate
fOUT = fXTAL x 227+NDIV / PHASE_RATE
0xA
0xA
0x20
0x20
0x6
0x6
0x20
Reserved
When written to 1, the PLL phase rate is
initialized with the initial phase rate register.
Self clearing.
Reserved
Fast Time Constant A Exponent
Reserved
Fast Time Constant B Exponent
Reserved
Fast Time Constant A Linear
Reserved
Fast Time Constant B Linear
Reserved
Slow Time Constant A Exponent
Reserved
Slow Time Constant B Exponent
Reserved
Slow Time Constant A Linear
20/88
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