ADE3000SX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3000SX Datasheet PDF : 88 Pages
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ADE3XXX
YUV Block
2.7 YUV Block
The TV video input module is used to interface external TV video decoder chip. It handles VESA
Video Interface Port(VIP) 8-bit/16-bit YCBCR, VMI/ ITU-R Recommendation 656 (CCIR656) YCBCR
and double clock edge input RGB data formats. It extracts embedded sync timing and converts data
into RGB color space. All the functions in this module are controlled by the system microcontroller
through I2C registers.
The following table describes the different pin configurations for YUV/RGB digital input.
Mode
CCIR656
VMI
VIP 8b
VIP 16b
RGB Posedge
RGB Negedge
YUV[7:0]
DATA[7:0]
DATA[7:0]
DATA[7:0]
DATA[7:0]
BLUE[7:0]
{RED[3:0],GREEN[7:4]}
TCON[3:0]
X
X
X
DATA[11:8]
GREEN[3:0]
RED[7:4]
TCON[7:4]
X
{HREF, VREF, VACTIVE, X}
X
DATA[15:12]
{HSYNC,VSYNC,DE,X}
{HSYNC,VSYNC,DE,X}
X = don’t care
Register Name
YUV_CTRL
YUV_STATUS
Table 11: YUV Registers (Sheet 1 of 2)
Addr
0x0700
0x0701
Mode Bits
[7:6]
R/W
[5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
[7]
R/W
[6]
R/W
[5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
Default
Description
Reserved
0x0
0: Rising edge of clock
1: Falling edge of clock
0x0
Input Source of Color Space Converter
0: YUV pins
1: ADC
0x0
Color Space Converter Enable
0x0
Sync Decoder Enable
0x0
Sample Input Data Rate
0:1x
1: 2x
0x0
Status Reset
Reserved
0x0
SAV detected
0x0
EAV detected
0x0
ANC detected
0x0
TASK detected
0x0
FIELDID detected
0x0
HSYNC detected
0x0
VSYNC detected
Writing to this register will clear all bits.
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