ADE3000SX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3000SX Datasheet PDF : 88 Pages
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Sync Retiming Block
Register Name
YUV_INT
ADE3XXX
Table 11: YUV Registers (Sheet 2 of 2)
Addr
0x0702
Mode Bits
[7:6]
R/W
[5]
R/W
[4:2]
R/W
[1]
R/W
[0]
Default
Description
Reserved
0x0
0: VIP 8b mode
1: VIP 16b mode (skip 1 clock after
every 6 valid data)
0x0
YUV data input format
0x2: YUV 16-bit
0x4: YUV 8-bit
0x6: RGB
all others: Reserved
0x0
0: C-Y
1: Y-C
0x0
0: Cr-Cb
1: Cb-Cr
2.8 Sync Retiming Block
The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into
the XCLK and INCLK domains.
For the XCLK domain, SRT has the following functionality:
q Retimes all sync signals going to SMEAS into the XCLK domain.
q Extracts vertical sync from composite sync signals (ahsync and acsync pins)
q Divides clocks by 1024 for activity detection purposes.
q Generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source.
q Generates a coast signal in the XCLK domain for the LLPLL.
Table 12: Sync Retiming Registers (Sheet 1 of 2)
Register Name
SRTXK_CSYNC_INV
SRTXK_SOG_THR_L
SRTXK_SOG_THR_H
SRTXK_CSYNC_THR_L
SRTXK_CSYNC_THR_H
Addr
0x01E0
0x01E1
0x01E2
0x01E3
0x01E4
Mode Bits
[7:3]
R/W
[2]
R/W
[1]
R/W
R/W
R/W
[0]
[7:0]
[7:4]
[3:0]
R/W
[7:0]
R/W
[7:4]
[3:0]
Default
Description
0x0
Reserved
0x0
invert filtered vert sync signal
0x0
invert composite sync signal
0x0
0x080
invert SOG signal
SOG vert sync extractor threshold [7:0]
Reserved
SOG vert sync extractor threshold [11:8]
0x080
composite sync vertical sync extractor
threshold [7:0]
Reserved
composite sync vertical sync extractor
threshold [11:8]
30/88
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