ADE3300 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3300 Datasheet PDF : 88 Pages
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ADE3XXX
Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 6 of 8)
Register Name
SMEAS_ANA_ACT
SMEAS_DVI_ACT
SMEAS_YUV_ACT
SMEAS_ANA_STUCK
SMEAS_DVI_STUCK
SMEAS_YUV_STUCK
SMEAS_XK_PER_H_L
SMEAS_XK_PER_H_M
SMEAS_XK_PER_H_H
SMEAS_XK_PER_V_L
SMEAS_XK_PER_V_M
SMEAS_XK_PER_V_H
Addr
0x0140
0x0141
0x0142
0x0143
0x0144
0x0145
0x0146
0x0147
0x0148
0x0149
0x014A
0x014B
Mode Bits Default
Description
[7:5] 0x0
Reserved
R
[4] 0x0
Composite sync is active
R
[3] 0x0
Vsync from SOG separator is active
R
[2] 0x0
Comp vsync from composite sync separator
is active
R
[1] 0x0
Analog hsync is active
R
[0] 0x0
Analog vsync is active
[7:2] 0x0
Reserved
R
[1] 0x0
DVI enable is active
R
[0] 0x0
DVI clk / 1K is active
[7:5] 0x0
Reserved
R
[4] 0x0
TCON vsync is active.
R
[3] 0x0
TCON hsync is active.
R
[2] 0x0
TCON enable is active.
R
[1] 0x0
YUV enable is active.
R
[0] 0x0
YUV clk / 1K is active.
[7:5] 0x0
Reserved
R
[4] 0x0
Comp sync is stuck at 1(high)/0(low)
R
[3] 0x0
Vsync from SOG separator is stuck at
1(high)/0(low)
R
[2] 0x0
Comp vsync from separator is stuck at
1(high)/0(low)
R
[1] 0x0
Analog hsync is stuck at 1(high)/0(low)
R
[0] 0x0
Analog vsync is stuck at 1(high)/0(low)
[7:2] 0x0
Reserved
R
[1] 0x0
DVI data enable is stuck at 1(high)/0(low)
R
[0] 0x0
DVI clk / 1K is stuck at 1(high)/0(low)
R
[7:5] 0x0
Reserved
R
[4] 0x0
TCON vsync is stuck at 1(high)/0(low)
R
[3] 0x0
TCON hsync is stuck at 1(high)/0(low)
R
[2] 0x0
TCON data enable is stuck at 1(high)/0(low)
R
[1] 0x0
YUV data enable is stuck at 1(high)/0(low)
R
[0] 0x0
YUV clk / 1K is stuck at 1(high)/0(low)
R
[7:0] 0x0
XCLKs per horizontal event - 1
R
[7:0] 0x0
R
[7:0] 0x0
R
[7:0] 0x0
XCLKs per vertical event - 1
R
[7:0] 0x0
R
[7:0] 0x0
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