Sync Mux Block
ADE3XXX
2.10
Sync Mux Block
The Sync Mux (SMUX) block provides the following functions:
q selects between all possible sync signals
q generates missing sync signals
q selects between original and generated signals for output
q generates the clamp signal for the ADC
Table 14: Sync Mux Registers (Sheet 1 of 2)
Register Name
SMUX_CTRL0
SMUX_CTRL1
Addr
0x0200
0x0201
Mode Bits Default
Description
R/W
R/W
R/W
R/W
[7] 0x0
[6] 0x0
[5] 0x0
[4] 0x0
R/W
[3:2] 0x0
R/W
[1:0] 0x0
R/W
R/W
R/W
[7:6] 0x0
[5] 0x0
[4] 0x0
[3] 0x0
R/W
[2] 0x0
R/W
[1] 0x0
R/W
[0] 0x0
Select TCON[7] as internal_hsync source.
Overrides SMUX_CTRL0[1:0] selection.
Select TCON[6] as internal_vsync source.
Overrides SMUX_CTRL0[3:2] selection.
Select TCON[5] as internal_enable source.
Overrides SMUX_CTRL0[4] selection.
Internal_enab select
0: DVI
1: YUV
Vsync_internal select
0x0: DVI
0x1: SRT vsync (normally analog)
0x2: YUVi
0x3: composite sync decoder
Hsync_internal select
0x0: DVI
0x1: LLK hsync (normally analog)
0x2: YUVi
0x3: raw vga hsync (may have jitter)
Reserved
Vsync_out invert
Hsync_out invert
V_reference edge select
0: falling
1: rising
V_reference select
0: venab_generated
1: vsync_internal
H_reference edge select
0: falling
1: rising
H_reference select
0: enab_internal
1: hsync_internal
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